SystemVerilog中数组的赋值、索引和切片

首先看下下面的这个示例：

module PU;
 int A[2:0][3:0][4:0], B[2:0][3:0][4:0], C[5:0][4:0];
 initial
 begin
    A[0][2][4] = 1024; //row 0, column 2, element #4
    //display index #4 (i.e., 5th element)
    $display("A[0][2][4]=",A[0][2][4]);
    //display 5 elements of row 0, column 2
    $display("A[0][2]=",A[0][2]);
 
    //display row 0 (4 columns; 5   elements each)
    $display("A[0]=",A[0]);
    //display 3 rows * 4 columns of 5 elements each
    $display("A=",A);
    $display("
");
    B[1][1][1]=512; //row 1; column 1; element #1
    // assign a subarray composed of fve ints
    A[2][3] = B[1][1];
    //display 5 elements of row 2, column 3
    $display("A[2][3]=",A[2][3]);
    B[0][0][0]=128; //Assign only to the last unpacked element
    A[1] = B[0];
    $display("
");
    $display("A[1]=",A[1]); //display row 1 (4 columns; 5 
elements each)
    C[5][4]=64;
    A[0][1] = C[5];
    $display("
");
    $display("C[5]=",C[5]);
    $display("A[0][1]=",A[0][1]);
 end
 endmodule

仿真log:

A[0][2][4]= 1024 //index #4 (i.e., 5th element)
A[0][2]='{1024, 0, 0, 0, 0} //5 elements of row 0, column 2
A[0]='{'{0, 0, 0, 0, 0}, '{1024, 0, 0, 0, 0}, '{0, 0, 0, 0, 0}, '{0, 0, 0, 0, 0}}
//4 columns of row 0 with value assigned to column 2, element #4 (5th position)
A='{'{'{0, 0, 0, 0, 0}, '{0, 0, 0, 0, 0}, '{0, 0, 0, 0, 0}, '{0, 0, 0, 0, 0}}, '{'{0, 0, 0, 0, 
0}, '{0, 0, 0, 0, 0}, '{0, 0, 0, 0, 0}, '{0, 0, 0, 0, 0}}, '{'{0, 0, 0, 0, 0}, '{1024, 0, 0, 
0, 0}, '{0, 0, 0, 0, 0}, '{0, 0, 0, 0, 0}}}
//Entire 3 rows*4 columns (12 entries – 5 elements each with value assigned to 
column 2, element #5)
A[2][3]='{0, 0, 0, 512, 0} // display 5 elements of row 2, column 3
A[1]='{'{0, 0, 0, 0, 0}, '{0, 0, 0, 0, 0}, '{0, 0, 0, 0, 0}, '{0, 0, 0, 0, 128}}
// display row 1 (4 columns; 5 elements each)
C[5]='{64, 0, 0, 0, 0} //Row 5, 5 elements with index 4 assigned

A[0][1]='{64, 0, 0, 0, 0} //Row 0, column 1 of 5 elements
V C S S i m u l a t i o n R e p o r t

Packed和Unpacked数组作为子程序的参数

数组可以作为参数传递给子程序，当数组作为值传递给子程序时，会将这个数组复制一份传递给子程序。

task trial (int a[3:1][3:1]); //’a’ is a two-dimensional array
 //(2-D unpacked)

上面是一个SystemVerilog task声明的示例，该task会将一个2维unpacked数组作为参数值传递。

int b[3:1][3:1]; // OK: same type, dimension, and size
 int b[1:3][0:2]; // OK: same type, dimension, & size
 // (different ranges)
 logic b[3:1][3:1]; // ERROR: incompatible element type
 // (logic vs. int)
 event b[3:1][3:1]; // ERROR: incompatible type (event 
vs. int)
 int b[3:1]; // ERROR: incompatible number of dimensions
 int b[3:1][4:1]; // ERROR: incompatible size (3 vs. 4)