强大的JTAG边界扫描2-BSDL文件

电子威廉希尔官方网站开发学习 2023-09-10 1114

描述

1. 什么是BSDL文件？

上一篇文章，我们介绍了JTAG边界扫描的基础知识，今天我们来看看边界扫描测试必须使用到的一个文件，BSDL文件。BSDL，Boundary Scan Description Language的缩写，即边界扫描描述语言，属于VHDL的一个子集，内容符合VHDL的语法标准，用于描述JTAG在指定设备中的实现方式，只要设备符合JTAG标准，那么它必须具有对应的BSDL文件。BSDL文件主要包括以下信息：

当前芯片所支持的最大TCK频率
定义了管脚的名称和序号
定义了电源、时钟、配置、IO管脚等等。每个管脚的类型，如VCC、GND、CLK，管脚的名称及序号
所有可用命令寄存器
所有可用的数据寄存器，包括可能的预设值，例如：器件的IDCODE

BSDL目前有两种标准IEEE 1149.1和IEEE 1149.6。IEEE 1149.6在IEEE 1149.1标准的基础上丰富了一些内容，它可以兼容IEEE 1149.1。

2. BSDL文件的获取

方式1：BSDL Library

https://www.bsdl.info/ 这个网站几乎包括所有支持JTAG芯片的BSDL文件，超过100家半导体公司的上万款芯片，包括MCU、DSP、PowerPC、CPLD、FPGA等，现在还在持续更新中。 vhdl

支持通过芯片型号或IDCODE搜索对应的BSDL文件，可以在线进行预览，非常方便 vhdl

方式2：各芯片的官方网站

在各大芯片厂商的官方网站一般会提供BSDL文件，下面以Xilinx、Altera、Microsemi、ST意法半导体为例，介绍如何获取BSDL文件。

Xilinx FPGA BSDL文件获取

Xilinx CPLD/FPGA BSDL文件一般位于开发环境ISE或Vivado安装路径下：ISE 14.7对应路径为，例如Artix-7系列XC7A100T的BSDL文件位于：

Xilinx14.7ISE_DSISEartix7data vhdl

Vivado 2018.3对应路径如下：

VivadoVivado2018.3ids_liteISEartix7data vhdl

除了开发环境的安装目录，Xilinx还在官方网站上提供有各系列FPGA的BSDL文件下载：

https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/device-models/bsdl-models/artix-series-fpgas.html

Altera FPGA BSDL文件获取

由于我的电脑没装Quartus开发环境，所以不确定BSDL文件是否能在安装路径下找到，Altera官方网站也可以进行下载：IEEE 1149.1 BSDL 文件下载

https://www.intel.cn/content/www/cn/zh/support/programmable/support-resources/board-layout/bsd-11491.html IEEE 1149.6 BSDL 文件下载

https://www.intel.cn/content/www/cn/zh/support/programmable/support-resources/board-layout/bsd-11496.html vhdl

Microsemi FPGA BSDL文件获取

Microchip（Microsemi）FPGA的BSDL模型下载地址：

https://www.microsemi.com/product-directory/design-resources/1717-bsdl-models vhdl

ST MCU BSDL文件获取

意法半导体MCU的BSDL文件可以到官方网站搜索BSDL，就会弹出对应系列的BSDL文件包。 vhdl

部分系列的BSDL文件下载地址：

STM32F1: https://www.st.com/content/ccc/resource/technical/ecad_models_and_symbols/bsdl_model/75/4a/50/d0/ad/aa/49/92/stm32f1_bsdl.zip/files/stm32f1_bsdl.zip/jcr:content/translations/en.stm32f1_bsdl.zip STM32F2: https://www.st.com/content/ccc/resource/technical/ecad_models_and_symbols/bsdl_model/e9/d6/86/75/13/99/46/c8/stm32f2_bsdl.zip/files/stm32f2_bsdl.zip/jcr:content/translations/en.stm32f2_bsdl.zip STM32F17: https://www.st.com/content/ccc/resource/technical/ecad_models_and_symbols/bsdl_model/ad/a6/69/0f/70/95/49/92/stm32f7_bsdl.zip/files/stm32f7_bsdl.zip/jcr:content/translations/en.stm32f7_bsdl.zip

3. BSDL文件示例

下面是Xilinx CPLD XC95144的BSDL文件的部分内容：

-- -- BSDL File created/edited by BCAD BSD Editor Version 3.1 -- --BSDE $Header: /devl/xcs/repo/env/Jobs/iMPACT/data/xc9500/xc95144.bsd,v 1.2 2000/10/24 0057 sanjays Exp $ --BSDE Xilinx 144 macrocell FastFLASH ISP CPLD entity XC95144 is generic (PHYSICAL_PIN_MAP : string := "DIE_BOND" ); port ( PB00_00: inout bit; PB00_01: inout bit; PB00_02: inout bit; ........ VSSINT_4: linkage bit; VSSIO_1: linkage bit; VSSIO_2: linkage bit; VSSIO_3: linkage bit; VSSIO_4: linkage bit; VSSIO_5: linkage bit; VSSIO_6: linkage bit; VSSIO_7: linkage bit; VSSIO_8: linkage bit; VSSIO_9: linkage bit ); use STD_1149_1_1990.all; attribute PIN_MAP of XC95144 : entity is PHYSICAL_PIN_MAP; constant DIE_BOND: PIN_MAP_STRING:= "PB00_00:PAD25," & "PB00_01:PAD18," & "PB00_02:PAD19," & "PB00_03:PAD27," & "PB00_04:PAD21," & "PB00_05:PAD22," & "PB00_06:PAD32," & "PB00_07:PAD23," & "PB00_08:PAD24," & "PB00_09:PAD34," & ........ "VSSIO_3:PAD51," & "VSSIO_4:PAD80," & "VSSIO_5:PAD99," & "VSSIO_6:PAD110," & "VSSIO_7:PAD120," & "VSSIO_8:PAD137," & "VSSIO_9:PAD160"; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (1.00e+07, BOTH); attribute INSTRUCTION_LENGTH of XC95144 : entity is 8; attribute INSTRUCTION_OPCODE of XC95144 : entity is "BYPASS ( 11111111)," & "CONLD ( 11110000)," & "EXTEST ( 00000000)," & "FERASE ( 11101100)," & "FBULK ( 11101101)," & "FPGM ( 11101010)," & "FPGMI ( 11101011)," & "FVFY ( 11101110)," & "FVFYI ( 11101111)," & "HIGHZ ( 11111100)," & "IDCODE ( 11111110)," & "INTEST ( 00000010)," & "ISCEN ( 11101000)," & "SAMPLE ( 00000001)," & "USERCODE ( 11111101)" ; attribute INSTRUCTION_CAPTURE of XC95144 : entity is "000XXX01"; attribute INSTRUCTION_DISABLE of XC95144 : entity is "HIGHZ"; attribute IDCODE_REGISTER of XC95144 : entity is "0010" & "1001010100001000" & "00001001001" & "1"; attribute USERCODE_REGISTER of XC95144 : entity is "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; attribute REGISTER_ACCESS of XC95144 : entity is "BYPASS ( CONLD, HIGHZ )," & "ISCENABLE[12] ( ISCEN)," & "ISCONFIGURATION[27] ( FERASE, FBULK, FPGM, FVFY)," & "ISCDATA[10] ( FPGMI, FVFYI)"; attribute BOUNDARY_CELLS of XC95144 : entity is " BC_1"; attribute BOUNDARY_LENGTH of XC95144 : entity is 432; attribute BOUNDARY_REGISTER of XC95144 : entity is " 0 (BC_1, *, internal, X)," & " 1 (BC_1, *, internal, X)," & " 2 (BC_1, *, internal, X)," & " 3 (BC_1, *, controlr, 0)," & " 4 (BC_1, PB07_16, output3, X, 3, 0, Z)," & " 5 (BC_1, PB07_16, input, X)," & " 6 (BC_1, *, controlr, 0)," & " 7 (BC_1, PB07_15, output3, X, 6, 0, Z)," & " 8 (BC_1, PB07_15, input, X)," & " 9 (BC_1, *, controlr, 0)," & " 10 (BC_1, PB07_14, output3, X, 9, 0, Z)," & ...省略部分... end XC95144;

4. BSDL文件的应用

BSDL文件可以在一些边界扫描的软件中被使用，如XJTAG，TopJTAG等等，通过加载对应的BSDL文件可以实现对芯片外部所有管脚的读取和控制。具体使用方法，我会在后面的文章介绍。 vhdl

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