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LMK04000,datasheet,pdf(Low-Noi
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2009-10-20
刘敏
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The LMK04000 family of precision clock conditioners provides
low-noise jitter cleaning, clock multiplication and distribution
without the need for high-performance voltage controlled
crystal oscillators (VCXO) module. Using a cascaded
PLLatinum™ architecture combined with an external crystal
and varactor diode, the LMK04000 family provides sub-200
femtosecond (fs) root mean square (RMS) jitter performance.
The cascaded architecture consists of two high-performance
phase-locked loops (PLL), a low-noise crystal oscillator circuit,
and a high-performance voltage controlled oscillator
(VCO). The first PLL (PLL1) provides a low-noise jitter cleaner
function while the second PLL (PLL2) performs the clock generation.
PLL1 can be configured to either work with an external
VCXO module or use the integrated crystal oscillator with
an external crystal and a varactor diode. When used with a
very narrow loop bandwidth, PLL1 uses the superior close-in
phase noise (offsets below 50 kHz) of the VCXO module or
the crystal to clean the input clock. The output of PLL1 is used
as the clean input reference to PLL2 where it locks the integrated
VCO. The loop bandwidth of PLL2 can be optimized
to clean the far-out phase noise (offsets above 50 kHz) where
the integrated VCO outperforms the VCXO module or crystal
used in PLL1.
low-noise jitter cleaning, clock multiplication and distribution
without the need for high-performance voltage controlled
crystal oscillators (VCXO) module. Using a cascaded
PLLatinum™ architecture combined with an external crystal
and varactor diode, the LMK04000 family provides sub-200
femtosecond (fs) root mean square (RMS) jitter performance.
The cascaded architecture consists of two high-performance
phase-locked loops (PLL), a low-noise crystal oscillator circuit,
and a high-performance voltage controlled oscillator
(VCO). The first PLL (PLL1) provides a low-noise jitter cleaner
function while the second PLL (PLL2) performs the clock generation.
PLL1 can be configured to either work with an external
VCXO module or use the integrated crystal oscillator with
an external crystal and a varactor diode. When used with a
very narrow loop bandwidth, PLL1 uses the superior close-in
phase noise (offsets below 50 kHz) of the VCXO module or
the crystal to clean the input clock. The output of PLL1 is used
as the clean input reference to PLL2 where it locks the integrated
VCO. The loop bandwidth of PLL2 can be optimized
to clean the far-out phase noise (offsets above 50 kHz) where
the integrated VCO outperforms the VCXO module or crystal
used in PLL1.
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