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gal16v8d pdf datasheet

消耗积分:10 | 格式:rar | 大小:555 | 2008-08-02

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The GAL16V8, at 3.5 ns maximum propagation delay time, combines
a high performance CMOS process with Electrically Erasable
(E2) floating gate technology to provide the highest speed
performance available in the PLD market. High speed erase times
(<100ms) allow the devices to be reprogrammed quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configurations
possible with the GAL16V8 are the PAL architectures listed
in the table of the macrocell description section. GAL16V8 devices
are capable of emulating any of these PAL architectures with full
function/fuse map/parametric compatibility.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and functionality
of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
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