资料下载
×
74HC646 pdf datasheet
消耗积分:3 |
格式:rar |
大小:133 |
2008-08-06
479809
分享资料个
MM54HC646/MM74HC646 Non-Inverting
Octal Bus Transceiver/Registers
MM54HC648/MM74HC648
Inverting Octal Bus Transceiver/Registers
General Description
These transceivers utilize advanced silicon-gate CMOS
technology, and contain two sets of TRI-STATEÉ outputs,
two sets of D-type flip-flops, and control circuitry designed
for high speed multiplexed transmission of data.
Six control inputs enable this device to be used as a latched
transceiver, unlatched transceiver, or a combination of both.
As a latched transceiver, data from one bus is stored for
later retrieval by the other bus. Alternately real time bus
data (unlatched) may be directly transferred from one bus to
another.
Circuit operation is determined by the G, DIR, CAB, CBA,
SAB, SBA control inputs. The enable input, G, controls
whether any bus outputs are enabled. The direction control,
DIR, determines which bus is enabled, and hence the direction
data flows: The SAB, SBA inputs control whether the
latched data (stored in D type flip flops), or the bus data
(from other bus input pins) is transferred. Each set of flipflops
has its own clock CAB, and CBA, for storing data. Data
is latched on the rising edge of the clock.
Each output can drive up to 15 low power Schottky TTL
loads. These devices are functionally and pin compatible to
their LS-TTL counterparts. All inputs are protected from
damage due to static discharge by diodes to VCC and
ground.
Features
Y Typical propagation delay: 14 ns
Y TRI-STATE outputs
Y Bidirectional communication
Y Wide power supply range: 2±6V
Y Low quiescent supply current: 160 mA
maximum (74HC)
Y High output current: 6 mA (74HC)
Octal Bus Transceiver/Registers
MM54HC648/MM74HC648
Inverting Octal Bus Transceiver/Registers
General Description
These transceivers utilize advanced silicon-gate CMOS
technology, and contain two sets of TRI-STATEÉ outputs,
two sets of D-type flip-flops, and control circuitry designed
for high speed multiplexed transmission of data.
Six control inputs enable this device to be used as a latched
transceiver, unlatched transceiver, or a combination of both.
As a latched transceiver, data from one bus is stored for
later retrieval by the other bus. Alternately real time bus
data (unlatched) may be directly transferred from one bus to
another.
Circuit operation is determined by the G, DIR, CAB, CBA,
SAB, SBA control inputs. The enable input, G, controls
whether any bus outputs are enabled. The direction control,
DIR, determines which bus is enabled, and hence the direction
data flows: The SAB, SBA inputs control whether the
latched data (stored in D type flip flops), or the bus data
(from other bus input pins) is transferred. Each set of flipflops
has its own clock CAB, and CBA, for storing data. Data
is latched on the rising edge of the clock.
Each output can drive up to 15 low power Schottky TTL
loads. These devices are functionally and pin compatible to
their LS-TTL counterparts. All inputs are protected from
damage due to static discharge by diodes to VCC and
ground.
Features
Y Typical propagation delay: 14 ns
Y TRI-STATE outputs
Y Bidirectional communication
Y Wide power supply range: 2±6V
Y Low quiescent supply current: 160 mA
maximum (74HC)
Y High output current: 6 mA (74HC)
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
评论(0)
发评论
- 相关下载
- 相关文章
