资料下载
×
HIP7020/HIP7020AP pdf datashee
消耗积分:3 |
格式:rar |
大小:555 |
2008-08-29
时见栖鸦
分享资料个
The HIP7020 IC is an Integrated I/O Bus Transceiver
designed for the SAE Standard J1850 Class B Data Communication
Network Interface. The Bus transmits and
receives data on a single wire using a 10.4kHz VPWM (Variable
Pulse Width Modulated) signal. The HIP7020 serves as
an I/O buffer interfacing to 5V CMOS logic. It is designed to
operate directly from the 12V battery line of an automobile.
The normal Bus voltage swing capability is from 0V to 7.75V
at currents greater than 20mA.
As shown in the Block Diagram, the Transmitter TX Input and
the Receiver RX Output of the Bus Transceiver Circuit interface
to the control logic. The TX input signal is wave shaped
for rise time, fall time and amplitude before it is converted
from voltage to current. The Wave Shaper with an external
programming resistor, RS controls the rise and fall time of
the BUS OUT output signal. The current source drive to the
Bus is voltage controlled by the Wave Shaped Voltage Reference
to a maximum limit as specified for the J1850 Bus and
includes short-circuit current limiting.
The HIP7020 Receiver input, BUS IN is connected to the
J1850 Bus through an external resistor, RF and has a trip
point at one-half of the nominal Bus signal voltage which is
3.875V. The Receiver input is filtered to remove high frequency
Bus noise by the external resistor and an internal
capacitor. The Receiver Bus signal, after processing, is output
at the RX pin by the RX Buffer’s open collector driver.
The RX output is active low and requires an external pull-up
resistor returned to the control logic VCC supply. This prevents
power-up of the control logic by the transceiver if VCC
supply voltage is removed.
designed for the SAE Standard J1850 Class B Data Communication
Network Interface. The Bus transmits and
receives data on a single wire using a 10.4kHz VPWM (Variable
Pulse Width Modulated) signal. The HIP7020 serves as
an I/O buffer interfacing to 5V CMOS logic. It is designed to
operate directly from the 12V battery line of an automobile.
The normal Bus voltage swing capability is from 0V to 7.75V
at currents greater than 20mA.
As shown in the Block Diagram, the Transmitter TX Input and
the Receiver RX Output of the Bus Transceiver Circuit interface
to the control logic. The TX input signal is wave shaped
for rise time, fall time and amplitude before it is converted
from voltage to current. The Wave Shaper with an external
programming resistor, RS controls the rise and fall time of
the BUS OUT output signal. The current source drive to the
Bus is voltage controlled by the Wave Shaped Voltage Reference
to a maximum limit as specified for the J1850 Bus and
includes short-circuit current limiting.
The HIP7020 Receiver input, BUS IN is connected to the
J1850 Bus through an external resistor, RF and has a trip
point at one-half of the nominal Bus signal voltage which is
3.875V. The Receiver input is filtered to remove high frequency
Bus noise by the external resistor and an internal
capacitor. The Receiver Bus signal, after processing, is output
at the RX pin by the RX Buffer’s open collector driver.
The RX output is active low and requires an external pull-up
resistor returned to the control logic VCC supply. This prevents
power-up of the control logic by the transceiver if VCC
supply voltage is removed.
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
评论(0)
发评论
- 相关下载
- 相关文章
