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SN74LVC1G373,pdf(Single D-Type

消耗积分:5 | 格式:rar | 大小:620 | 2010-08-02

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This single D-type latch is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

While the latch-enable (LE) input is high, the Q output follows the data (D) input. When LE is taken low, the Q output is latched at the logic level set up at the D input.

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OE does not affect the internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

A buffered output-enable (OE) input can be used to place the output in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the output neither loads nor drives the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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