Altera Stratix IV GT 100G开发方案

关键词： ALTERA , Stratix IV GT 100G

Altera公司的Stratix IV 40nm FPGA包括Stratix IV E, Stratix IV GX和Stratix IV GT三个系列, 具有最高的密度(680K 逻辑单元(LE),22.4 Mbits 嵌入式存储器和1,360个18 x 18 乘法器),最佳的性能以及最低的功耗, 系统带宽(8.5 Gbps的48 个高速收发器，以及 1,067 Mbps (533 MHz) DDR3存储器接口)达到了前所未有的水平，并具有优异的信号完整性, 非常适合无线通信,固网,军事,广播等其他最终市场中的高端数字应用。本文介绍了Stratix® IV FPGA主要特性, Stratix IV GT器件框图,以及采用EP4S100G5F45I1 Stratix IV GT FPGA器件的Stratix IV GT 100G开发板主要特性,方框图,详细威廉希尔官方网站 图和材料清单.

Altera® Stratix® IV FPGAs deliver a breakthrough level of system bandwidth and power efficiency for high-end applications, allowing you to innovate without compromise. Stratix IV FPGAs are based on the Taiwan Semiconductor Manufacturing Company (TSMC) 40-nm process technology and surpass all other high-end FPGAs, with the highest logic density, most transceivers, and lowest power requirements.

The Stratix IV device family contains three optimized variants to meet different application requirements:

■ Stratix IV E (Enhanced) FPGAs—up to 813,050 logic elements (LEs), 33,294 kilobits
(Kb) RAM, and 1,288 18 x 18 bit multipliers

■ Stratix IV GX transceiver FPGAs—up to 531,200 LEs, 27,376 Kb RAM, 1,288 18 x 18-bit multipliers, and 48 full-duplex clock data recovery (CDR)-based transceivers at up to 8.5 Gbps

■ Stratix IV GT—up to 531,200 LEs, 27,376 Kb RAM, 1,288 18 x 18-bit multipliers, and 48 full-duplex CDR-based transceivers at up to 11.3 Gbps

Stratix® IV FPGA主要特性:

The following list summarizes the Stratix IV device family features:

■ Up to 48 full-duplex CDR-based transceivers in Stratix IV GX and GT devices supporting data rates up to 8.5 Gbps and 11.3 Gbps, respectively

■ Dedicated circuitry to support physical layer functionality for popular serial protocols, such as PCI Express (PCIe) (PIPE) Gen1 and Gen2, Gbps Ethernet (GbE), Serial RapidIO, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI, Fibre Channel, SFI-5, and Interlaken

■ Complete PCIe protocol solution with embedded PCIe hard IP blocks that implement PHY-MAC layer, Data Link layer, and Transaction layer functionality

■ Programmable transmitter pre-emphasis and receiver equalization circuitry to compensate for frequency-dependent losses in the physical medium

■ Typical physical medium attachment (PMA) power consumption of 100 mW at 3.125 Gbps and 135 mW at 6.375 Gbps per channel

■ 72,600 to 813,050 equivalent LEs per device

■ 7,370 to 33,294 Kb of enhanced TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and FIFO buffers

■ High-speed digital signal processing (DSP) blocks configurable as 9 x 9-bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full-precision multipliers at up to 600 MHz

■ Up to 16 global clocks (GCLK), 88 regional clocks (RCLK), and 132 periphery clocks (PCLK) per device

■ Programmable power technology that minimizes power while maximizing device performance

■ Up to 1,120 user I/O pins arranged in 24 modular I/O banks that support a wide range of single-ended and differential I/O standards

■ Support for high-speed external memory interfaces including DDR, DDR2, DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 24 modular I/O banks

■ High-speed LVDS I/O support with serializer/deserializer (SERDES), dynamic phase alignment (DPA), and soft-CDR circuitry at data rates up to 1.6 Gbps

■ Support for source-synchronous bus standards, including SGMII, GbE, SPI-4 Phase 2 (POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1

■ Pinouts for Stratix IV E devices designed to allow migration of designs from Stratix III to Stratix IV E with minimal PCB impact

Stratix IV GT Devices

Stratix IV GT devices provide up to 48 CDR-based transceiver channels per device:

■ Thirty-two out of the 48 transceiver channels have dedicated PCS and PMA circuitry and support data rates between 600 Mbps and 11.3 Gbps

■ The remaining 16 transceiver channels have dedicated PMA-only circuitry and support data rates between 600 Mbps and 6.5 Gbps

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图1. Stratix IV GT器件框图
Stratix IV GT器件主要特性:

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采用EP4S100G5F45I1 Stratix IV GT FPGA器件的Stratix IV GT 100G开发板
Stratix IV GT 器件EP4S100G5F45I1主要特性:

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The Stratix IV GT 100G development board provides a hardware platform for evaluating the performance and signal integrity features of the Altera® Stratix IV GT devices.

Altera的Stratix® IV GT版100G开发套件支持您对100GbE设计进行全面评估：

通过光模块，支持10G/40G和100G线路接口。

通过4x18 ADRII和4x32 DDR3存储器块，支持需要外部存储器接口的应用。

通过两对FCI AirMax连接器，使用系统侧接口。

全面的线路侧(光模块)至系统侧(AirMax连接器)数据通路分析。

评估性能高达11.3 Gbps的收发器。

验证兼容10G/40G/100G以太网、Interlaken、CEI-6G/11G、PCI Express (Gen1, Gen2和Gen3)、Serial RapidIO®以及其他主要标准的物理介质附加(PMA)子层。

验证SFP、SFP+、QSFP和CFP等光模块之间的互操作性。

Stratix IV GT版100G开发套件包括：

Stratix IV GT开发板(参见图1)

安装的器件：EP4S100G5F45I1N

EPM2210F324C3N，MAX® II 256引脚CPLD

配置状态和设置单元

快速被动并行(FPP)配置

嵌入式USB-BlasterTM下载电缆

时钟

板上可编程时钟振荡器

SMA连接器，为收发器参考时钟提供外部差分时钟。

通用用户输入/输出

DIP和按键式开关

LED

LCD

存储器件

1-Gb同步闪存(主要用于存储两个FPGA配置——工厂和用户配置)

板上存储器

4个2-Gb DDR3 SDRAM

4个72-Mb QDR II SRAM

元件和接口

10/100/1000以太网PHY和RJ-45插头

36个收发器通道

1个SFP+接口通道

1个具有EDC的SFP+接口通道

4个QSFP接口通道

10个CFP接口通道

20个Interlaken接口通道

温度测量威廉希尔官方网站

管芯温度

环境温度

电源

14-V至20-V直流输入

2.5-mm筒形插座，用于直流电源输入。

On/off电源滑动开关

板上电源测量威廉希尔官方网站

Quartus II软件许可并没有含在这一套件中

You can use this development kit to:

• Develop and test designs to interface with a variety of different optical modules.

• Develop and test Interlaken designs.

• Develop and test memory subsystems consisting of DDR3 or QDR II memory.

• Build designs capable of migrating to Altera’s HardCopy IV ASICs.

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图2.Stratix IV GT 100G开发板方框图

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图3.Stratix IV GT 100G开发板外形图

Stratix IV GT 100G开发板威廉希尔官方网站 图见:

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Stratix IV GT 100G开发板威廉希尔官方网站 图.pdf (1.74 MB, 下载次数: 0)

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Stratix IV GT 100G开发板材料清单见:

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Stratix IV GT 100G开发板材料清单.rar (20.85 KB, 下载次数: 0)

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