我要做基于
FPGA的模数转换算法设计，采用的是顶层设计，分模块编写，再
元件例化。ad部分没问题，就是fpga里把16位二进制数转换成32位单精度浮点数并做除法，编译之后错误都出现在fpga模块里和顶层设计的有关fpga的语句里，还都是语法错误。请教大神指导修改，谢谢！
顶层设计：
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;
EN
tiTY test IS
port(
led_out:out std_logic;
clk1: IN std_logic;
HOLDA,HOLDB,HOLDC:OUT std_logic;
S3_rd,S2_rd,S1_rd:OUT std_logic;
S3_CS,S2_CS,S1_CS:OUT std_logic;
S3_EOC,S2_EOC,S1_EOC:IN std_logic;
data_bus: out std_logic_vector (15 downto 0);
reset_bar: IN std_logic
);
END entity test;
Architecture behavioral of test is
component ads8365 is
port (
a1: IN std_logic;
HOLDA1,HOLDB1,HOLDC1:OUT std_logic;
S3_rd1,S2_rd1,S1_rd1:OUT std_logic;
S3_CS1,S2_CS1,S1_CS1:OUT std_logic;
S3_EOC1,S2_EOC1,S1_EOC1:IN std_logic;
data_bus1: out std_logic_vector (15 downto 0);
reset_bar1: IN std_logic
);
end component;
component fpga is
port (reset_bar2: IN std_logic;
clk_f: IN std_logic;
aaa1: out std_logic_vector(31 downto 0);
aaa2: out std_logic_vector(31 downto 0)
);
end component;
component led_out is
port (led_out1:out std_logic;
clkin: IN std_logic
);
end component;
signal AD_ctr_reg: std_logic_vector(15 downto 0);--ADC control regester
signal AD_EOC_reg: std_logic_vector(15 downto 0);-- ADC end convered regesiter
signal ab_rege_cs1: std_logic;
signal Addr_reg: std_logic_vector(15 downto 0);--address regestor
signal clk_test: std_logic;
signal a_delayed: std_logic;
signal a_pe: std_logic;
signal Retifier_sector_reg: std_logic_vector(5 downto 0);
signal Retif_deadtimer: std_logic_vector(15 downto 0);
signal Inverter_sector_reg: std_logic_vector(5 downto 0);
signal Inverter_deadtimer: std_logic_vector(15 downto 0);
signal sap: std_logic;
signal ***p: std_logic;
signal scp: std_logic;
begin
u1: component ads8365 port map (a1=> clk1,HOLDA1=> HOLDA,HOLDB1=> HOLDB,HOLDC1=> HOLDC,
S3_rd1=> S3_rd,S2_rd1=> S2_rd,S1_rd1=> S1_rd,S3_CS1=> S3_CS,S2_CS1=> S2_CS,S1_CS1=> S1_CS,
S3_EOC1=> S3_EOC,S2_EOC1=> S2_EOC,S1_EOC1=> S1_EOC,data_bus1=> data_bus,reset_bar1=> reset_bar
);
u2: component fpga port map (reset_bar2=> reset_bar,clk_f=> clk1);
u3: component led_out port map (led_out1=> led_out,clkin=> clk1);
end behavioral;
fpga模块：
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;
entity fpga is
port ( reset_bar2: IN std_logic;
clk_f: IN std_logic;
aaa1: out std_logic_vector(31 downto 0 );
aaa2: out std_logic_vector(31 downto 0)
);
end entity fpga;
Architecture behavioral of fpga is
signal Addr_reg: std_logic_vector(15 downto 0);
signal AD_ctr_reg: std_logic_vector(15 downto 0);
signal s1:std_logic;
signal s2:std_logic;
signal m1:std_logic_vector(22 downto 0);
signal m2:std_logic_vector(22 downto 0);
signal e1:std_logic_vector(7 downto 0);
signal e2:std_logic_vector(7 downto 0);
begin
process(a1)
variable a1_counter3:integer range 0 to 20;
begin
if reset_bar2 = '0'then
a1_counter3 :=0;
elsif rising_edge(a1) then
if a1_counter3 =20 then
a1_counter3 :=0;
temp:= Addr_reg xor "0111111111111111";
temp:= conv_std_logic_vector(conv_integer(temp)+1,16);
aaa1(31)<= 0;
aaa1(30 DOWNTO 23)<= 10001110;
aaa1(22 DOWNTO 0) <= temp (14 downto 0) & "00000000";
s1<=aaa1(31);
e1<=aaa1(30 DOWNTO 23);
m1<=aaa1(22 DOWNTO 0);
aaa2(31)<= 0;
aaa2(30 downto 23)<= 10001100;
aaa2(22 downto 0) <= "1001100110011" & "0000000000";
s2<=aaa2(31);
e2<=aaa2(30 DOWNTO 23);
m2<=aaa2(22 DOWNTO 0);
else
a1_counter3:=a1_counter3+1;
end if;
end if;
END PROCESS;
end;
