module control_cnt(clk_100hz,reset,on_off,pause);
input clk_100hz,reset,on_off;
output reg pause;
reg [1:0] current_state;
reg [1:0] next_state;
parameter [1:0] clear=2'b00;
parameter [1:0] on=2'b01;
parameter [1:0] off=2'b10;
always@(posedge clk_100hz or negedge reset)
begin
if(!reset)
current_state<=clear;
else
current_state<=next_state;
end
always@(current_state or on_off or reset)
begin
case(current_state)
clear:
begin
if(!reset)
begin
next_state=clear;
pause=0;
end
else
begin
if(on_off)
begin
next_state=on;
pause=1;
end
else
begin
next_state=clear;
pause=0;
end
end
end
on:
begin
if(!reset)
begin
next_state=clear;
pause=0;
end
else
begin
if(on_off)
begin
next_state=off;
pause=0;
end
else
begin
next_state=on;
pause=1;
end
end
end
off:
begin
if(!reset)
begin
next_state=clear;
pause=0;
end
else
begin
if(on_off)
begin
next_state=on;
pause=1;
end
else
begin
next_state=off;
pause=0;
end
end
end
default: next_state=off;
endcase
end
endmodule
最后用了状态机控制输出pause信号,同一个非自锁开关按键作开始和暂停键,低电平表示开始,高电平表示暂停
module control_cnt(clk_100hz,reset,on_off,pause);
input clk_100hz,reset,on_off;
output reg pause;
reg [1:0] current_state;
reg [1:0] next_state;
parameter [1:0] clear=2'b00;
parameter [1:0] on=2'b01;
parameter [1:0] off=2'b10;
always@(posedge clk_100hz or negedge reset)
begin
if(!reset)
current_state<=clear;
else
current_state<=next_state;
end
always@(current_state or on_off or reset)
begin
case(current_state)
clear:
begin
if(!reset)
begin
next_state=clear;
pause=0;
end
else
begin
if(on_off)
begin
next_state=on;
pause=1;
end
else
begin
next_state=clear;
pause=0;
end
end
end
on:
begin
if(!reset)
begin
next_state=clear;
pause=0;
end
else
begin
if(on_off)
begin
next_state=off;
pause=0;
end
else
begin
next_state=on;
pause=1;
end
end
end
off:
begin
if(!reset)
begin
next_state=clear;
pause=0;
end
else
begin
if(on_off)
begin
next_state=on;
pause=1;
end
else
begin
next_state=off;
pause=0;
end
end
end
default: next_state=off;
endcase
end
endmodule
最后用了状态机控制输出pause信号,同一个非自锁开关按键作开始和暂停键,低电平表示开始,高电平表示暂停
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