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FPGA接DM8147 VIP0的portA 16bit discreate模式capture_link无法接收到数据，请问这个问题怎么解决？

本帖最后由 一只耳朵怪 于 2018-5-29 11:22 编辑

DM8147 VIP0的portA接FPGA无法接收到数据。
我们使用FPGA接4个AP0101，把四个数据通过FPGA合成一个之后通过VIP0的portA传给DM8147的HDVPSS，我们将ISS的初始化代码注释了，但是现在capturelink一直采集不到数据，请大神帮忙分析一下原因。
开发包IPNC_RDK3.5
现在我们用FPGA输出YUV数据，使用16根数据线，输入格式为SYSTEM_DF_YUV422P    SYSTEM_STD_1080P_30 使用CLK HSYNC

以下是对程序的修改：
【ipnc_rdk中修改的内容】
文件captureLink_drv.c
Int32 CaptureLink_drvCreateInst(CaptureLink_Obj * pObj, UInt16 instid)
[
。。。

pVipCreateArgs->videoCaptureMode = VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_HSYNC_VSYNC;
pVipCreateArgs->videoIfMode = VPS_CAPT_VIDEO_IF_MODE_16BIT;

。。。
]
并将system_m3vpss.c文件中Int32 System_init()中有关iss的代码都注释掉
【HDVPSS中修改的内容】
文件：vpsdrv_captureVip.c中修改的内容（函数Vps_captVipParserConfigSetup中）
vipPortConfig->disConfig.fidDetectMode = VPS_VIP_FID_DETECT_MODE_VSYNC;//zzh
vipPortConfig->disConfig.actvidPol = VPS_VIP_POLARITY_HIGH;
vipPortConfig->disConfig.vsyncPol = VPS_VIP_POLARITY_HIGH;
vipPortConfig->disConfig.hsyncPol = VPS_VIP_POLARITY_HIGH;



usecase:
CaptureLink_CreateParams_Init(&capturePrm);
capturePrm.numVipInst = 1; //1个采集口
//capturePrm.outQueParams[0].nextLink = nNullID;
capturePrm.outQueParams[0].nextLink = gVencModuleContext.ipcM3OutId;//gVcapModuleContext.nsfId[0];// gMultiCh_VsrcVencObj.ipcOutVpssId;////下一个linkID
capturePrm.tilerEnable = FALSE; //停用tiler
capturePrm.fakeHdMode = FALSE; //是否启用模拟1080P输出
capturePrm.enableSdCrop = FALSE; //是否启用裁剪 采集为D1时有用 将720裁剪为704
capturePrm.doCropInCapture = FALSE; //是否启用裁剪 采集为D1时有用 将720裁剪为704 通过调整指针的方式实现 //采集通道参数设置
for(vipInstId=0; vipInstId [
pCaptureInstPrm = &capturePrm.vipInst[vipInstId];
pCaptureInstPrm->vipInstId = (SYSTEM_CAPTURE_INST_VIP0_PORTA+vipInstId)%SYSTEM_CAPTURE_INST_MAX;/*ID设置*/
pCaptureInstPrm->videoDecoderId = 0; /* Need to change based on actual HD video decoder */
pCaptureInstPrm->inDataFormat = SYSTEM_DF_YUV422P;//SYSTEM_DF_YUV422I_YUYV;
//pCaptureInstPrm->standard = SYSTEM_STD_1944P_14;
pCaptureInstPrm->standard = SYSTEM_STD_1080P_30; /* Need to change based on actual HD video decoder */
pCaptureInstPrm->numOutput = 1; /* Need to change based on actual HD video decoder */
pCaptureOutPrm = &pCaptureInstPrm->outParams[0];
pCaptureOutPrm->dataFormat = SYSTEM_DF_YUV420SP_UV;//SYSTEM_DF_YUV420SP_UV;//
pCaptureOutPrm->scEnable = FALSE; /* Need to change based on actual HD video decoder */
pCaptureOutPrm->scOutWidth = 1920; /* Need to change based on actual HD video decoder */
pCaptureOutPrm->scOutHeight = 1080; /* Need to change based on actual HD video decoder */
pCaptureOutPrm->outQueId = 0;
]
设备启动时的打印信息
********** FULL FEATURE USECASE ********
[host] ********* Entered MultiCh_createTriStreamFullFtr ********

[host] 143: MCFW : CPU Revision [ES2.1] !!!
[host] 144: MCFW : Detected [UNKNOWN] Board !!!
[host] 144: MCFW : Base Board Revision [REV A] !!!
[m3vpss ] VPS_DCTRL_INST_0
[m3vpss ] IOCTL_VPS_DCTRL_SET_VENC_OUTPUT SYSTEM_DC_VENC_DVO2
[m3vpss ] IOCTL_VPS_DCTRL_SET_VENC_OUTPUT SYSTEM_DC_VENC_HDMI
[m3vpss ] IOCTL_VPS_DCTRL_SET_VENC_OUTPUT SYSTEM_DC_VENC_SD
[m3vpss ] IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC VPS_DC_VENC_HDMI | VPS_DC_VENC_DVO2
[m3vpss ] 11676: CAPTURE: Create in progress !!!
[m3vpss ] Vps_captCreate ## start ...
[m3vpss ] ################## pInstPrm->standard : default
[m3vpss ] 11714: CAPTURE: VIP0 PortA capture mode is [16-bit, Non-mux Discrete Sync - ACTVID_VSYNC] !!!
[m3vpss ] Vps_captCreate ## start ...
[m3vpss ] Vps_captCreate ## 1
[m3vpss ] Vps_captCreate ## 2
[m3vpss ] Vps_captCreate ## 3
[m3vpss ] Vps_captCreate ## 4
[m3vpss ] Vps_captCreate ## 5
[m3vpss ] Vps_captCreate ## 6
[m3vpss ] Vps_captCreate ## 7
[m3vpss ] Vcore_vipResAllocPath ### input source is single-channel YUV422 ...
[m3vpss ] Vps_captCreateChObj ## VPDMA CH ID vChannelId[0]:104
[m3vpss ] Vps_captCreateChObj ## VPDMA CH ID vChannelId[1]:105
[m3vpss ] Vps_captCreate ## 7 - 1
[m3vpss ] ----------------------------------------------------
[m3vpss ] drivers/capture/src/vpsdrv_captureVip.c:334
[m3vpss ] vipInstConfig->intfMode : 1
[m3vpss ] vipInstConfig->vipConfig.clipActive : 0
[m3vpss ] vipInstConfig->vipConfig.clipBlank : 0
[m3vpss ] ----------------------------------------------------
[m3vpss ] vipPortConfig->syncType : 4
[m3vpss ] vipPortConfig->ctrlChanSel : 1
[m3vpss ] vipPortConfig->ancChSel8b : 0
[m3vpss ] vipPortConfig->pixClkEdgePol : 0
[m3vpss ] vipPortConfig->invertFidPol : 0
[m3vpss ] vipPortConfig->invertFidPol : 0
[m3vpss ] vipPortConfig->enablePort : 1
[m3vpss ] vipPortConfig->clrAsyncFifoRd : 0
[m3vpss ] vipPortConfig->clrAsyncFifoWr : 0
[m3vpss ] vipPortConfig->discreteBasicMode : 1
[m3vpss ] ----------------------------------------------------
[m3vpss ] vipPortConfig->disConfig.fidSkewPostCnt : 0
[m3vpss ] vipPortConfig->disConfig.fidSkewPreCnt : 0
[m3vpss ] vipPortConfig->disConfig.lineCaptureStyle : 1
[m3vpss ] vipPortConfig->disConfig.fidDetectMode : 1
[m3vpss ] vipPortConfig->disConfig.actvidPol : 1
[m3vpss ] vipPortConfig->disConfig.vsyncPol : 1
[m3vpss ] vipPortConfig->disConfig.hsyncPol : 1
[m3vpss ] ----------------------------------------------------
[m3vpss ] Vps_captCreate ## 7 - 2
[m3vpss ] Vps_captCreate ## 7 - 3
[m3vpss ] Vps_captCreate ## 7 - 4
[m3vpss ] Vps_captCreate ## 7 - 5
[m3vpss ] Vps_captCreate ## 7 - 6
[m3vpss ] Vps_captCreate ## 7 - 7
[m3vpss ] Vps_captCreate ## 7 - 8
[m3vpss ] Vps_captCreate ## 8
[m3vpss ] Disable VIP cropping ## 393:Vps_captCreate
[m3vpss ] Vps_captCreate ## end ...
[host] IPCBitsInLink_tskMain:Entered
[host] 556: IPC_BITS_IN : Create in progress !!!
[host] 556: IPC_BITS_IN : ListMPOpen start !!!
[host] 556: SYSTEM: Opening ListMP [VIDEO-M3_IPC_OUT_28] ...
[m3video] 11974: IPC_IN_M3 : Create in progress !!!
[m3video] 11974: SYSTEM: Opening ListMP [VPSS-M3_IPC_OUT_0] ...
[m3video] 11975: SYSTEM: Opening ListMP [VPSS-M3_IPC_IN_0] ...
[m3vpss ] CAPTURE::HEAPID:0 USED:192
[m3video] 11978: IPC_IN_M3 : Create Done !!!
[m3vpss ] 11970: CAPTURE: Create Done !!!
[m3video] 11978: ENCODE: Create in progress ... !!!
[m3vpss ] 11971: IPC_OUT_M3 : Create in progress !!!
[m3video] 12007: ENCODE: Creating CH0 of 1920 x 1080, pitch = (1920, 1920) [PROGRESSIVE] [NON-TILED ], bitrate = 8000 Kbps ...
[m3vpss ] numCh: 0,frameSkipCtx.inputFrameRate: 30,frameSkipCtx.outputFrameRate:30
[m3vpss ] bufType = 0
[m3vpss ] codingformat = 0
[m3video] ENCLINK_H264:HEAPID:0 USED:13808
[m3vpss ] dataFormat = 7
[m3video] 12071: ENCODE: All CH Create ... DONE !!!
[m3vpss ] memType = 0
[m3vpss ] startX = 0
[m3vpss ] startY = 0
[m3video] ENCLINK:HEAPID:0 USED:14048
[m3vpss ] width = 1920
[m3video] 12074: ENCODE: Create ... DONE !!!
[m3vpss ] height = 1080
[m3video] 12074: IPC_BITS_OUT : Create in progress !!!
[m3vpss ] pitch[0] = 1920
[m3vpss ] pitch[1] = 1920
[m3vpss ] pitch[2] = 0
[m3video] 12077: IPC_BITS_OUT : Create Done !!!
[m3vpss ] scanFormat = 1
[m3vpss ] 11973: IPC_OUT_M3 : Create Done !!!

回帖（9）

乔婧

2018-5-28 03:57:24
Liu Jiang,
请问你是否有测量过FPGA输出时钟，同步信号是否正常？你是否有修改过时钟，同步信号的极性，看是否有帮助?
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赵敏

2018-5-28 04:07:48
引用: 物是人非aaa 发表于 2018-5-28 03:57
Liu Jiang,
请问你是否有测量过FPGA输出时钟，同步信号是否正常？你是否有修改过时钟，同步信号的极性，看是否有帮助?

谢谢您的回复！
我们测试了FPGA的数据，FPGA 时钟为74.25MHz 使用CLK VSYNC HSYNC D[0-15]信号线，VSYNC和HSYNC都为高时数据有效。输出的视频为1920*1080 30帧
现在找到之前采集不到数据的原因了： 我在Vps_captIsrListComplete()回调函数中添加了打印信息。去掉之后就有数据了。
--------------------------------------------------------------------------------------------------------------------------------------
回到函数所在文件vpsdrv_captureList.c
/* Driver callback called by CLM with timer expires */
Void Vps_captIsrListComplete()
[
/* get current time */
gVps_captCommonObj.clockTicks = Clock_getTicks();
##########################去除的打印##############################
// Vps_printf ( " %s:%d: Driver callback called by CLM with timer expires !!!n",
// __FUNCTION__, __LINE__);
##########################去除的打印##############################
/* trigger list processing task */
Semaphore_post(gVps_captCommonObj.semListUpdate);
]
--------------------------------------------------------------------------------------------------------------------------------------
但是我们有遇到两个新的问题：
1.captureLink采集的过程中会出现数据帧中的pFrame->reserved>0的问题，所以程序一直提示【[m3vpss ] 247926: CAPTURE: Dequeued frame more than once (0,0, b90f6e80)】。我们跟踪了一下代码发现好像是video 中H264压缩部分将pFrame->reserved设置为了当前时间，这个该如何解决啊？
2.第二个问题是，如果设备上电FPGA在HDVPSS初始化之前就给数据信号的话，也会没有采集。我们将FPGA中加了100秒的延迟，在HDVPSS初始化完成之后FPGA再给数据信号（时钟信号一直在给）就能够正常采集。这可能是什么原因导致的？


问题1的错误提示在文件 captureLink_drc.c 中的CaptureLink_drvProcessData函数
Int32 CaptureLink_drvProcessData(CaptureLink_Obj * pObj)
[
                    ...
                   tmpValue = (UInt32) pFrame->reserved;
                   if (tmpValue > 0)
                   [
                            Vps_printf
                                     (" %d: CAPTURE: Dequeued frame more than once (%d,%d, %08x) n",
                                     Utils_getCurTimeInMsec(), queId, queChId, pFrame->addr[0][0]);
                   ]
                  tmpValue++;
                  pFrame->reserved = (Ptr) tmpValue;
                 ...
]
问题1的错误提示：

[m3vpss ] 247926: CAPTURE: Dequeued frame more than once (0,0, b90f6e80)
[m3vpss ] 247966: CAPTURE: Dequeued frame more than once (0,0, b93ee480)
[m3vpss ] 247998: CAPTURE: Dequeued frame more than once (0,0, b96e5a80)
[m3vpss ] 248030: CAPTURE: Dequeued frame more than once (0,0, b99dd080)
[m3vpss ] 248062: CAPTURE: Dequeued frame more than once (0,0, b9cd4680)
[m3vpss ] 248094: CAPTURE: Dequeued frame more than once (0,0, b9fcbc80)
[m3vpss ] 248126: CAPTURE: Dequeued frame more than once (0,0, ba2c3280)
[m3vpss ] 248166: CAPTURE: Dequeued frame more than once (0,0, ba5ba880)
[m3vpss ] 248198: CAPTURE: Dequeued frame more than once (0,0, ba8b1e80)
[m3vpss ] 248230: CAPTURE: Dequeued frame more than once (0,0, b8810c80)
[m3vpss ] 248262: CAPTURE: Dequeued frame more than once (0,0, b8b08280)
[m3vpss ] 248294: CAPTURE: Dequeued frame more than once (0,0, b8dff880)
[m3vpss ] 248326: CAPTURE: Dequeued frame more than once (0,0, b90f6e80)
[m3vpss ] 248366: CAPTURE: Dequeued frame more than once (0,0, b93ee480)
[m3vpss ] 248398: CAPTURE: Dequeued frame more than once (0,0, b96e5a80)
[m3vpss ] 248430: CAPTURE: Dequeued frame more than once (0,0, b99dd080)
[m3vpss ] 248462: CAPTURE: Dequeued frame more than once (0,0, b9cd4680)
[m3vpss ] 248494: CAPTURE: Dequeued frame more than once (0,0, b9fcbc80)
[m3vpss ] 248526: CAPTURE: Dequeued frame more than once (0,0, ba2c3280)
[m3vpss ] 248566: CAPTURE: Dequeued frame more than once (0,0, ba5ba880)
[m3vpss ] 248598: CAPTURE: Dequeued frame more than once (0,0, ba8b1e80)
[m3vpss ] 248630: CAPTURE: Dequeued frame more than once (0,0, b8810c80)
[m3vpss ] 248662: CAPTURE: Dequeued frame more than once (0,0, b8b08280)
[m3vpss ] 248694: CAPTURE: Dequeued frame more than once (0,0, b8dff880)
[m3vpss ] 248726: CAPTURE: Dequeued frame more than once (0,0, b90f6e80)
[m3vpss ] 248766: CAPTURE: Dequeued frame more than once (0,0, b93ee480)
举报

赵敏

2018-5-28 04:25:09
引用: 物是人非aaa 发表于 2018-5-28 03:57
Liu Jiang,
请问你是否有测量过FPGA输出时钟，同步信号是否正常？你是否有修改过时钟，同步信号的极性，看是否有帮助?

针对之前的问题2我们使用CCS查看了vin的寄存器值

FPGA有延迟时，HDVPSS初始化之后FPGA再给数据信号。可以正常采集。
FPGA没有延迟时，上电之后HDVPSS初始化之前就给数据信号，出现如图中的寄存器不同，提示output FIFO PortA Luma Overflow。我们在设备程序启动之后添加了调用采集部分重启的命令IOCTL_VPS_CAPT_RESET_AND_RESTART还是不行。这个问题该如何解决呢？
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葛睿洁

2018-5-28 04:37:57
引用: 神秘司令 发表于 2018-5-28 04:07
谢谢您的回复！
我们测试了FPGA的数据，FPGA 时钟为74.25MHz 使用CLK VSYNC HSYNC D[0-15]信号线，VSYNC和HSYNC都为高时数据有效。输出的视频为1920*1080 30帧
现在找到之前采集不到数据的原因了： 我在Vps_captIsrListComplete()回调函数中添加了打印信息。去掉之后就有数据了。

          你的fpga的输出是按照cea-861，参考标准时序输出的吗？
        你可以试一下修改采集模式：
pVipCreateArgs->videoCaptureMode =
VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_ACTVID_VSYNC;
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