#include
#include
#include "cslr/cslr_cache.h"
#include
#include
void config_cache(void);
int test_config(void);
int testResult=0; // Test status
int main(void)
[
// Configure the cache using register layer
config_cache();
// Verify configuration using the Cache module api's
return(test_config());
]
void config_cache(void)
[
CSL_CacheRegsOvly cacheRegs = (CSL_CacheRegsOvly)CSL_CACHE_0_REGS;
volatile unsigned int stall;
// The below writes to the CFG registers are followed by a dummy read. Mode
// switches require that a read is performed immediately after the write. The
// read stalls the cpu to ensure the mode change completes.
// Set L1P size to 32K
CSL_FINST(cacheRegs->L1PCFG,CACHE_L1PCFG_MODE,32K);
stall = cacheRegs->L1PCFG;
// Set L1D size to 32K
CSL_FINST(cacheRegs->L1DCFG,CACHE_L1DCFG_MODE,32K);
stall = cacheRegs->L1DCFG;
// Set L2 size to 64k and normal opperation
cacheRegs->L2CFG = CSL_FMKT(CACHE_L2CFG_MODE,64K)
| CSL_FMKT(CACHE_L2CFG_L2CC,NORMAL);
stall = cacheRegs->L2CFG;
// The MAR registers set the cachability of memory spaces external to the
// megamodule. Below is an example of turning on cachability for two ranges.
// Reference spru871H for a complete list the MAR ranges.
// Set MAR[192] range 0xC0000000-0xC0FFFFFF as cacheable
CSL_FINST(cacheRegs->MAR[192],CACHE_MAR_PC,CACHEABLE);
]
int test_config(void)
[
Cache_Size checkSize;
Cache_Mode checkMode;
Cache_Mar checkMar192;
Ptr baseMar192;
baseMar192 = (Ptr)0xC0000000; // MAR192 base address
// The Cache module read API's are used to verify the previous configuration
// that was performed using the register layer.
// Read L1P, L1D, and L2 cache size settings
Cache_getSize(&checkSize);
// Read L2 mode setting
checkMode = Cache_getMode(Cache_Type_L2);
// Read MAR192 setting
checkMar192 = Cache_getMar(baseMar192);
printf("nTest cache configuratonn");
// Verify cache size settings for L1P, L1D, and L2
if((checkSize.l1pSize==Cache_L1Size_32K)&&(checkSize.l1dSize==Cache_L1Size_32K)&&
(checkSize.l2Size==Cache_L2Size_64K))
[
printf("nL1P size = 32Kn");
printf("L1D size = 32Kn");
printf("L2 size = 64Kn");
]
else
[
printf("nError setting cache sizesn");
testResult=1;
]
// Verify mode setting for L2
if(checkMode==Cache_Mode_NORMAL)
printf("nL2 mode set to NORMALn");
else
[
printf("nError setting moden");
testResult=1;
]
// Verify MAR192 settings
if(checkMar192==Cache_Mar_ENABLE)
printf("nMAR192 range set to cacheablen");
else
[
printf("nError setting MAR rangen");
testResult=1;
]
// Display test status
if(testResult==0)
printf("nCache configuration test: PASSEDn");
else
printf("nCache configuration test: FAILEDn");
return(testResult);
]
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