大家好
我是使用实例化基元的管道连接的新手
我实现了一个完整的组合设计，其中我实例化了LUT和carry4瞬间，然后我在顶层实体的输入端口注册了两个寄存器级的所有输入和输出，在顶层实体输出处注册了两个寄存器级，然后我启用了寄存器平衡和检查
优化实例化的预置。
合成过程正确传递但是当我运行翻译过程时，错误出现与实例化的LUT相关
这是错误：
错误：NgdBuild：455 - 逻辑网络“Add_Rnd / Correct_B”有多个驱动程序：块Add_Rnd / Correct_B1上的引脚O，类型为LUT5，引脚PAD上的块为Add_Rnd / Correct_B，类型为PAD
错误：NgdBuild：924 - 输入焊盘网'Add_Rnd / Correct_B'驱动非缓冲原语：块状地址为Add_Rnd / DigitSum / LUT4_inst上的引脚I1，类型为LUT4，引脚I1位于块Add_Rnd / DigitSum / LUT5_inst上，类型为LUT5，引脚O开启
块类型为LUT5的Add_Rnd / Correct_B1，类型为LUT6的块Add_Rnd / SelectS0OrS1227上的引脚I2，类型为LUT6的块Add_Rnd / SelectS0OrS1113_F上的引脚I2，类型为LUT6的块Add_Rnd / SelectS0OrS1113_G上的引脚I3
我是否需要实例化一个额外的组件，以便该工具可以管道这些LUT？!!!!!!
我还在层次结构中实现了一个较小的实体，我在其中实例化LUT并且没有出现此错误..那么为什么这会发生在顶级设计实体中？
恐怕这是工具的一个bug :(
我使用的是ISE12.1
先谢谢了
以上来自于谷歌翻译
以下为原文
Hi all
I am new with using the pipelinning of instan
tiated primitives
I have implemented a full combination design in which i instantiated LUT's and carry4 instants then i registered all inputs and outputs with two register stages at input ports of the top entity and two register stages at the top entity outputs then i enabled the register balancing and checked the optimize instantiated premitives.
the syntyhesis process passed correctly but when i run the translate process an Error appears related to the instantiated LUT's
and here is the Error :
ERROR:NgdBuild:455 - logical net 'Add_Rnd/Correct_B<10>' has multiple driver(s):
pin O on block Add_Rnd/Correct_B<10>1 with type LUT5,
pin PAD on block Add_Rnd/Correct_B<10> with type PAD
ERROR:NgdBuild:924 - input pad net 'Add_Rnd/Correct_B<10>' is driving non-buffer
primitives:
pin I1 on block Add_Rnd/DigitSum/LUT4_inst with type LUT4,
pin I1 on block Add_Rnd/DigitSum/LUT5_inst with type LUT5,
pin O on block Add_Rnd/Correct_B<10>1 with type LUT5,
pin I2 on block Add_Rnd/SelectS0OrS1<0>227 with type LUT6,
pin I2 on block Add_Rnd/SelectS0OrS1<0>113_F with type LUT6,
pin I3 on block Add_Rnd/SelectS0OrS1<0>113_G with type LUT6
Do i need to instantiated an additional component so that the tool can pipeline these LUT's ?!!!!!!
I also implemented a smaller entity in the hierarchy in which i instantiate LUT's and this error did not appear .. then why this happened with the top design entity ?!!!! Am afraid this is a bug with the tool :(
Am using ISE12.1
Thanks in advance :D
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