VHDL中的二维数组怎么实现

如果可能的话，坚持使用一个HDL会更容易。
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

It would be easier to stick to one HDL if at all possible.
------------------------------------------
"If it don't work in simulation, it won't work on the board."

好。
但是从顶层文件中访问其他组件的内存（数组）的过程是什么？
有害生物风险分析
有害生物风险分析



以下为原文

Ok.
But what is the procedure to access the memory (array) in the top file from other components?
Pras
Pras

我不确定你实际上在做什么以及在什么情况下。在VHDL中你不能通过其实体的端口访问其他架构内的信号。
Verilog不是那么严格。假设VHDL，你需要设计访问结构，使你能够编写和读取内存数组。
或者您可以使用LogiCore构建一个内存组件，其中定义了端口和使用情况。您之前是否完成了数字设计？
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

I'm not sure what you are actually trying to do and in what context.

In VHDL you cannot access signals inside other architectures except via their entity's ports. Verilog is not so strict.

Assuming VHDL, you need to design access structures to enable you to write and read the memory array. Or you could use LogiCore to build you a memory component that has the ports and usage thereof defined.

Have you done digital design before?

------------------------------------------
"If it don't work in simulation, it won't work on the board."

你在vhdl的经历是什么？
你能写一个矢量模块吗？



以下为原文

what is your experiance in vhdl ?
 
can you write a single vector module ?