怎么延迟PWM带宽为100MHz

嗨，我会延迟PWM带宽为100MHz，周期为2e-6秒（2微秒）。
总延迟时间为1e-6秒。我将使用具有250 MHz或320 MHz时钟的FPGA来构建这样的移位寄存器：
PWM输入为“数据输入”，时钟是异步的。
我选择一个足够快的时钟来“采样”输入。
时钟更快= PWM的宽度更精确。
根据时钟速度，DFF的数量为250或320，以获得1微秒的延迟。
我可以使用Spartan-3A likeXC3S50A-4TQG144C或XC3S50A-4TQG144I完成这项工作吗？
他们内部有足够的大门来完成这项工作吗？
任何人都有更好的想法来完成这项工作？
谢谢和最诚挚的问候。

以上来自于谷歌翻译

以下为原文

Hi,
I would delay PWM with a 100MHz bandwith, and a period of 2e-6 seconds (two microseconds) . the total amount of delay is 1e-6 seconds.
I would use an FPGA with a 250 MHz or 320 MHz clock, to build a shift register like this one:

The PWM input is "Data in", and the clock is asyncronous. I choose a clock fast enough to "sample" the input. Faster the clock = more accurate the width of the PWM.

The number of DFF is 250 or 320 accordingly with the clock speed, to obtain 1 microsecond delay.
I could do this job with a Spartan-3A like XC3S50A-4TQG144C or XC3S50A-4TQG144I?
They have enough gates, inside, to do the job?
Anyone have a better idea to do the job?

Thanks and Best Regards.

陈舒斌

2019-2-14 11:35:44

嗨，
实际上，你需要用于这种移位寄存器的触发器，而不是门。
而且，是的，甚至在像3S50这样的小型设备中也有很多它们。
每个slioce有两个FF。
但是，如果延迟是恒定的，那么有更多的资源保存方法。
一个是LUT可以用作16级移位寄存器，所以
每个LUT 320级/ 16级= 20 LUT
这是一个非常小的（现在）逻辑资源。
理论上不需要专用的FF，而你应该在输入上使用至少两个，在输出上使用一个来过滤亚稳态事件和改进的路由（例如使用IOB FF）。
Xilinx的一些应用笔记告诉您如何充分利用LUTS作为移位寄存器的详细信息。
有一个很好的综合
Eilert

以上来自于谷歌翻译

以下为原文

Hi,
actually, you need flipflops for such a shift register, not gates.
And, yes, there's plenty of them even in a small device like the 3S50. Each slioce has two FFs.

However, if the delay is intended to be constant, there are more ressource saving approaches.
One is that LUTs can be used as 16 stage shift registers, so
320 Stages / 16 Stages per LUT = 20 LUTs
which is a really small ammount of (now) logic ressources.
No dedicated FF needed theoretically, while you should use at least two on the input and one on the output for filtering metastability events and improved routing (e.g. using IOB FFs).
There are several application notes from Xilinx telling you details on how to make best use of LUTS as shift registers.

Have a nice synthesis
Eilert