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数字设计的VHDL代码中乘法运算符用途是什么?

HII
实际上我想知道数字设计的VHDL代码中乘法运算符(MOD REM)的确切用途是什么?
为什么它包含在这种语言中
..

以上来自于谷歌翻译


以下为原文

hii
actually i want to know waht is exact use of multiplying operator ( MOD  REM )   in VHDL codes or digital desing ?
why it is included in this language
..

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李华

2019-2-18 13:19:24
模数运算符,可应用于整数类型。表达式“A mod B”的结果是整数类型,并定义为以下值:
(1)(A mod B)的符号与B的符号相同,并且

(2)abs(A mod B)以下为原文

The modulus operator which can be applied to integer types.  The result of the expression "A mod B" is an integer type and is defined to be the value such that:
 
(1)  the sign of (A mod B) is the same as the sign of B, and
(2)  abs (A mod B) < abs (B), and
(3)  (A mod B) = (A * (B - N)) for some integer N
 
example:
6 mod 4 : 2
6 mod -4 : -2
-6 mod 4 : 2


 
The remainder operator which can be applied to integer types.  The result of the expression "A rem B" is an integer type and is defined to be the value such that:
 
(1)  the sign of (A rem B) is the same as the sign of A, and
(2)  abs (A rem B) < abs (B), and
(3)  (A rem B) = (A - (A / B) * B).
 
Example:
6 mod 4 : 2
6 mod -4 : -2
-6 mod 4 : 2


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陈舒斌

2019-2-18 13:35:53
嗨,
为什么MOD​​和RAM包含在任何语言中?
也许这些运算符在处理有界数字字段时非常有用。
例如
你有一些有限的记忆。
现在你想通过一些大型的滚动计数器来循环它。
即使是范围整数在超出边界时也会产生溢出,而不是像从位向量中知道的那样滚动到0。
因此,您需要一些执行此操作的功能,并且MOD和REM是要使用的功能。
您可能会反对在综合代码中使用整数类型并不是一个好主意。
(至少不适合初学者。)
同意,但VHDL不仅仅是综合。
有许多行为仿真模型和测试平台不必遵守综合标准的限制。
只需查看XilinxCoreLib源代码即可查看应用示例。
这可以帮助您找到这些文件和行:
yourpath ... / ISE_DS / ISE / vhdl / src / XilinxCoreLib)$ grep“mod”*
有一个很好的综合 
Eilert

以上来自于谷歌翻译


以下为原文

Hi,
why are MOD and RAM included in any language?
 
Maybe these operators are quite useful when working with bounded numerical fields.
 
e.g. you have some memory of limited size.
Now you want to adress it cyclic by some large rolling counter.
Even ranged integers create an overflow when incremented beyond their borders, instead of rolling over to 0 like you know it from bit vectors.
So you need some function that performs this operation and there MOD and REM are the ones to use.
 
You may object that it's no good idea to use integer types in synthesis code. (At least not for beginners.)
Agreed, but VHDL is more than just synthesis.
There are a lot of behavioral simulation models and testbenches which do not have to obey the limitations of the synthesis standard.
Just take a look at XilinxCoreLib sources to see application examples.
This may help you finding these files and lines:
yourpath.../ISE_DS/ISE/vhdl/src/XilinxCoreLib)$ grep "mod " *
 
Have a nice synthesis
  Eilert
 
 
 
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张桂兰

2019-2-18 13:52:31
以上来自于谷歌翻译


以下为原文

 
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张桂兰

2019-2-18 14:03:10
谢谢... EILERT

以上来自于谷歌翻译


以下为原文

thanks... EILERT
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