可以在EDK中使用Axi4Stream接口/总线吗？

你好，
我正在EDK中使用axi4stream。
有人可以帮助我如何使用通过Vivado高级综合（HLS）生成的ap_fifo / axi4stream接口可以在EDK中使用吗？
我正在使用Export Rtl：PCore for EDK。
细节：
我使用Vivado HLS来合成64个元素的离散余弦变换。
void dct_hw_sep_io_stub（int pBaseMatrix [64]，int result [64]）
核心有两个端口，一个64个整数/元素的输入数组（合成为ap_memory），输出端口合成为ap_fifo。
我使用Axi4Lite / Slave向顶级模块发出指令，以便将生成的IP与Zynq Processing System连接起来。
现在，为了将数据发送到corfe并收回，Vivado hls将输入端口合成为ap_memory（这意味着为输入端口pBaseMatrix []合成了内存），输出端口合成为ap_fifo，这意味着，
由于AXi4Lite不支持fifo结构，因此只能使用AXI4Stream接口/总线从输出端口result []读取数据。
我也是这个嵌入式总线和接口世界的新手
。
vivado hls用户指南（Ug902）告诉我，对于ap_memory它不需要总线进行通信，而是一个bram控制器可以完成将数据“馈送”到输入的工作，所以我添加了一个Bram控制器IP（不确定如果我连接
它正确，请参阅附加的图片）。
但是，要读取模块的输出，我需要一个AXI4Stream接口。在EDK中，我找不到AXI4Stream IP，或者可能是我之前没有使用过edk，之前，我对edk比较新。
EDK_ctt.pdf指南没有解释我如何构建axi4stream接口。
无论如何，我必须连接我的result []输出并从中读取数据。
我无法理解如何读取和写入我从Vivado Hls生成的模块的数据。
有人可以告诉我如何将Zynq PS（独立）连接到我的模块，以及AXI4stream的参考API以及之后的AXI4Lite API吗？
非常感谢期待！我读了Xapp745：处理器控制Vhls .pdf，它只讲述了标量输入/输出端口。
以下是完整edk项目（通过PlanAhead调用）...和mpd文件的端口和总线接口视图的屏幕截图，如有必要。
最好，
Rahman Mehboob
dct_hw_sep_io_stub_top_v2_1_0.mhs 5 KB



以下为原文

Hello,
I am struggling using axi4stream in EDK. Can somebody help me how I can use an ap_fifo/axi4stream interface generated through Vivado High Level Synthesis (HLS) can be used in EDK? I am using Export Rtl: PCore for EDK.

Details:
I used Vivado HLS to synthesize a Discrete Cosine Transform of 64 elements.
void dct_hw_sep_io_stub( int pBaseMatrix[64],int result[64] )

The core has two ports, one input array of 64 integers/elements (which is synthesized as ap_memory), and the output port which is synthesized as ap_fifo. I put a directive to the top level module with Axi4Lite/Slave, so as to connect the generated IP with Zynq Processing System. Now, in order to send the data to the corfe and take back, the Vivado hls synthesized the input port as ap_memory (which means a memory is synthesized for the input port pBaseMatrix[]), and the output port as ap_fifo, which means, only AXI4Stream interface/bus can be used to read the data from the output port result[] as AXi4Lite does not support fifo structures. I am new to this embedded world of buses and interfaces, too)
.
vivado hls user guide (Ug902) tells that for ap_memory it does not need a bus to communicate, rather a bram controller can do the job for 'feeding' data to the input, So I added a Bram Controller IP (not sure If I connected it correctly, see the attached pics). However, to read output from the module, I need an AXI4Stream interface. In EDK, I can not find an AXI4Stream IP, or may be I have not used edk much, before, I am relatively new to edk. the EDK_ctt.pdf guide does not explain how i can build an axi4stream interface. In any case, I have to connect my result[] output and read data from it. I am at a loss to understand how I can read and write data to the module I generated from Vivado Hls..

Can Somebody please tell me how I can connect Zynq PS (standalone) to my module, and the reference APIs for AXI4stream as well AXI4Lite APIs afterwards? Many thanks in anticipation!! I read the Xapp745:Processor control Vhls .pdf, which only tells about scalar inputs/output ports.

Here are the screen shots for the ports and bus interface view for the complete edk project (invoked through PlanAhead).., and mpd file, if necessary.





Best,
Rahman Mehboob
            dct_hw_sep_io_stub_top_v2_1_0.mhs ‏5 KB