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[问答]

怎么在Verilog HDL实现对称舍入?

嗨,
乘数IP在virtex中有输出舍入,但在斯巴达中没有。
如果我想用Verilog HDL实现roundinglikevirtexIP。怎么样?
谢谢!

以上来自于谷歌翻译


以下为原文

Hi,
    The multiplier IP have output rounding in virtex,but not in spartan.
    If I want to realize the rounding like virtex IP using Verilog HDL. How?
    Thanks!

回帖(1)

朱寅竹

2019-3-1 08:45:28
看看这里的一些提示:
http://www.xilinx.com/support/documentation/user_guides/ug193.pdf
“在向无穷大对称舍入时,CARRYIN位设置为结果的符号位栏。
这确保了中点负数和正数都从零开始舍入。
例如,2.5轮到3轮和-2.5轮到-3轮。
在对称舍入为零时,CARRYIN位设置为结果的符号位。
中点处的正数和负数舍入为零。
例如,2.5轮到2轮和-2.5轮到-2轮。“
对称舍入的谷歌搜索也会产生很多结果
www.xilinx.com

以上来自于谷歌翻译


以下为原文

Have a look here for some tips:
http://www.xilinx.com/support/documentation/user_guides/ug193.pdf
 
"In symmetric rounding towards infinity, the CARRYIN bit is set to the sign bit bar of the result. 
This ensures that the midpoint negative and positive numbers are both rounded away
from zero. For example, 2.5 rounds to 3 and -2.5 rounds to -3. In symmetric rounding towards
zero, the CARRYIN bit is set to the sign bit of the result. Positive and negative numbers at
the midpoint are rounded towards zero. For example, 2.5 rounds to 2 and -2.5 rounds to -
2."
 
A google search on symmetric rounding will turn up a lot of results as well
www.xilinx.com
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