没有时钟校正

嗨，
您是否在谈论xilinx提供的IP，其CLKCORCNT状态为000？
当RX弹性缓冲器等待时间太高或太低时，触发时钟校正，并且时钟校正威廉希尔官方网站 检测到匹配序列。
可能延迟不是太高而且clkcorcnt还没有触发时钟校正状态。
但是，您的设计中的数据接收有任何问题吗？
谢谢，AnirudhPS：请将此标记作为答案，以防它有助于解决您的问题。如果帖子引导您找到解决方案，请给予赞誉。



以下为原文

Hi,
 
Are you talking about the IP provided by xilinx has the CLKCORCNT status given as 000?
 
Clock correction is triggered when the RX elastic buffer latency is too high or too low, and the clock correction circuit detects a match sequence. Probably the latency was not too high and the clkcorcnt has not yet triggered the clock correction state.
 
However do you have any problem in data reception in your design?
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.

你好，
感谢您的回复。
您是否在谈论xilinx提供的IP，其CLKCORCNT状态为000？
是
但是，您的设计中的数据接收有任何问题吗？
是的，在gmii_rxd中我无法接收任何数据。
我可以收到配置order_set。
只是这个！
我可以在gmii_rxd中看到下面的字符串。
谢谢



以下为原文

Hello,
Thanks for your reply.
 
Are you talking about the IP provided by xilinx has the CLKCORCNT status given as 000?
 
YES
 
However do you have any problem in data reception in your design?
 
Yes, in gmii_rxd I can't receive any data. I can just receive configuration order_set. Just this!
Just I can see the below string in gmii_rxd.
 

 
Thanks
 

嗨@hupaa，
如果您想测试GT，那么您可以直接使用IBERT测试进行检查。
这将排除任何时钟同步问题。
你究竟使用什么核心。
基于此，我可以将此问题发送给正确的董事会或人员，以便他们可以提供帮助。
谢谢，AnirudhPS：请将此标记作为答案，以防它有助于解决您的问题。如果帖子引导您找到解决方案，请给予赞誉。



以下为原文

Hi @hupaa ,
 
In case you want to test the GT, then you can directly check using the IBERT test. This would rule out any clock synchronization issues. What core are you using exactly. Based on this i can route this issue to the correct board or person so that they can help.
 
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.

HelloAnirudh，
感谢您的回复。
我用iBERT测试了GT。
一切都好。
但现在，我想在网卡（ENW-9701）和FPGA（KC705板上的Kintex7）之间建立连接。
我想从网卡上收到一些数据。
我在chipcope中检查它们。
支持的协议isieee802.3。
在FPGA中生成的核心是Ethernet1000BASE-X PCS / PMA或SGMII IPCore。
在这个核心中，嵌入了7Series FPGA TransceiversWizard IPCore，但您可以自己生成GTX收发器核心而不是嵌入式核心。
我做到了。
你能指导我吗？
谢谢



以下为原文

Hello Anirudh,
Thanks for your reply.
I've tested the GT with iBERT. Everything is OK.
But now, I want to have a connection between a network card(ENW-9701) and the FPGA(Kintex7 on KC705 board). 
I want to receive some data from network card. I'm checking them in chipscope.
Supported protocol is ieee802.3 .
The core that was generated in FPGA is Ethernet1000BASE-X PCS/PMA or SGMII IPCore. In this core, the  7Series FPGAs Transceivers Wizard IPCore was embedded,but you can generate GTX transceiver core by yourself and put instead of embedded core. and I'v done it. 
Could you please guide me?
 
Thanks