找不到DDR2信号

我生成了DDR2设计但是当我在硬件上运行它时，led_error输出总是很高，表明读回失败。
为了缩小问题范围，我需要查看接口中的总线传输，但是当我尝试将chipcope信号挂钩到DDR2总线实现失败时。
如果我查看发送的数据和数据从内存中读回并存储在fifo中，chipcope cdc会导致时序约束失败并且还会改变设计的时序性能，因此我无法捕获可靠的数据。
我尝试将DDR2信号路由到另一组I / O，以便我可以将它们连接到外部逻辑分析仪板，但是再次实现失败，说它在设计中找不到DDR2信号（???）。
有谁知道可能会发生什么以及探测DDR2总线以便调试的可靠方法？消息由shrutiparashar编辑于07-23-2009 05:50 PM



以下为原文

I generated a DDR2 design but when I run it on hardware the led_error output is always high indicating a failure in read back. In order to narrow down the issue I need to look at bus transfer in interface but when I try to hook chipscope signals up to DDR2 bus implementation fails. If I look at sent data and data read back from memory and stored in fifo, the chipscope cdc causes timing constraints to fail and also alters the timing performance of design, so I haven't been able to capture reliable data. I tried routing DDR2 signals to another set of I/O so that I can connect them to external logic analyser pad, but again implementation fails saying it couldn't find DDR2 signals in the design(???). Does anyone know what could be going on and what is a reliable way to probe DDR2 bus in order to debug?Message Edited by shrutiparashar on  07-23-2009 05:50 PM