Verilog寄存器初始化没有复位引脚

XST将根据Verilog标准自动为您初始化变量。
所以，在过去，
我做过以下代码：
reg [15：0] rst_pipe = 16'hffff;
wire reset = rst_pipe [15];
永远@（posedge clk） 
rst_pipe
约翰普罗塞纳
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以下为原文

XST will automatically initialize variables for you as per the Verilog standards.  So, in the past,
I've done code like:
 
reg [15:0] rst_pipe = 16'hffff;
wire reset = rst_pipe[15];
 
always @(posedge clk)
  rst_pipe <= {rst_pipe, 1'b0};
 
Everytime the design is reloaded, the signal reset will be asserted for 16 clock cycles at the start.
 
Note that ASIC designs don't allow this, this is a feature of FPGAs.
 
John Providenza
View solution in original post

杰米，
GSR特定于我们的设备，因此为了使用它，您必须完全按照指定实例化基元。
除非您特别要求，否则通用HDL代码将无法理解您想要做什么。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

Jamie,
 
GSR is specific to our devices, so in order to use it, you must instatiate the primitives exactly as specified.

Generic HDL code will not understand what you want to do, unless you specifically request it.
 
Austin Lesea
Principal Engineer
Xilinx San Jose

嗨奥斯汀，
感谢你的回答。
我知道GSR特定于Xilinx，我很高兴在设计中使用许多系统级原语，如GSR。
我想要避免的是为设计中的每个寄存器使用实例化的基元。
因此，只要我能用“posedge clock”样式块定义寄存器，即使我需要其他编译器指令，我也会很高兴。
没有复位引脚有没有办法做到这一点？
问候，
杰米



以下为原文

Hi Austin,
 
Thanks for the answer.  I am aware that GSR is Xilinx specific and am happy to use a number of system-level primitives such as GSR in the design.  What I want to avoid is the use of instantiated primitives for every single register in the design.  So as long as I can define the register with a "posedge clock" style block even I need other compiler directives I would be happy.  Is there a way to do this without a reset pin?
 
Regards,
Jamie

XST将根据Verilog标准自动为您初始化变量。
所以，在过去，
我做过以下代码：
reg [15：0] rst_pipe = 16'hffff;
wire reset = rst_pipe [15];
永远@（posedge clk） 
rst_pipe
约翰普罗塞纳



以下为原文

XST will automatically initialize variables for you as per the Verilog standards.  So, in the past,
I've done code like:
 
reg [15:0] rst_pipe = 16'hffff;
wire reset = rst_pipe[15];
 
always @(posedge clk)
  rst_pipe <= {rst_pipe, 1'b0};
 
Everytime the design is reloaded, the signal reset will be asserted for 16 clock cycles at the start.
 
Note that ASIC designs don't allow this, this is a feature of FPGAs.
 
John Providenza