请问怎么同时使用ADC和DAC？

你好
我认为它们不能同时使用，因为SPI总线（MOSI，MISO，SCK）信号是共享的。
有关详细信息，请参阅Spartan-3E FPGA入门工具包用户指南的第9章和第10章：http：//www.xilinx.com/support/documentation/boards_and_kits/ug230.pdf。
因此，您必须使用某种机制，例如交替启用和禁用这些设备，以及使用内存来存储从ADC捕获的样本。
这是我的想法。
因为你使用过ADC，我对它的操作有疑问：当我加载Amp时。
通过其8位定标设置并将CS / LD引脚置为1，该模式信号捕获期间该引脚必须为1，或者在将比例设置加载到Amp后将其返回到零。
???
（在我的项目中，我需要以恒定的增益记录整个信号）。
OMS



以下为原文

Hello
 
i think they can not be used as the same time because the SPI bus (MOSI , MISO , SCK) signals are shared .
 
for more details see chapter 9 and 10 of Spartan-3E FPGA Starter Kit Board User Guide : http://www.xilinx.com/support/documentation/boards_and_kits/ug230.pdf .
 so you must use a certain mechanism like enabling and desabling these devices alternately and to use a memory to store the sample that captured from ADC .
This is my idea about that.
because you was used the ADC , I have a question on its operation : when i load the Amp. with its 8 bit scaling setting and assert the CS/LD pin to 1 , Is this pin must 1 during analog signal capturing or to return it to zero after scale setting has been loaded to Amp. ???
( in my project i need to record the whole signal in a constant gain ).
 
oms

你也可以给我发一个VHDL代码，用于通过Amp从头J7捕获模拟信号。
和ADC，
我也有一个斯巴达3E入门套件。
谢谢
OMS



以下为原文

also can you send me a VHDL code for capturing an analog signal  from header J7 via the Amp. and ADC ,
i have a spartan 3E starter kit too.
 
Thanks
oms

试试这个核心......
我不久前开发了它....
还有一个ADC / AMP测试平台
adc.rar 5 KB



以下为原文

Try this core...
 
I developed it some times ago....
 
there is also a testbench for ADC/AMP
            adc.rar ‏5 KB

亲爱的alexgiul，
非常感谢玩具回答我。
。
。
我读了你的代码，我有以下问题： -
1.此代码是否在spartan3E stater kit上实现？
2.在ADC / AMP.vhd代码的以下部分： -
if index1 = 13 thenADC1（index1）elseADC1（index1）end if; index1：= index1 -1; sample
为什么你采用每个样本的第一位捕获（m***）的补码（标记为粗体字），这个IF的功能是什么？
3. SCK不得超过10 MHz来设置AMP增益（参见http://www.xilinx.com/support/documentation/boards_and_kits/ug230.pdf的第10章），我认为它在代码中更高。
4. state_type中以下首字母缩写词（HI，LO）的长名称是什么？
你可以将以下翻译成英文，请： -  
* inizio a campionare。 
* LO_UMMY中的ci passo una solavoltadobodichèlaassegno。 
* rappresentazione in complemento a 2。
最后，我非常感谢你。
。
。
谢谢。
OMS



以下为原文

Dear alexgiul,
Thank toy very much for answering me . . .
 
I was read your code and i have the following questions :-
 
1. Is this code implemented on spartan3E stater kit befor ?
 
2. In the follwoing part of ADC/AMP.vhd code :-
if index1 = 13 then
      ADC1(index1)  <= not SPI_MISO;
     else
      ADC1(index1)  <= SPI_MISO;
     end if;     
     index1 := index1 -1;
     sample <='1';
Why you take the complement of the first bit captured (m***) of each sample (marked as bold font), what is the function of this IF ?
 
3. The SCK must not exceed the 10 MHz for setting the AMP gain (see chapter 10 of  http://www.xilinx.com/support/documentation/boards_and_kits/ug230.pdf) , and i think it higher in your code .
 
4.What is the long name of the following acronyms ( HI , LO ) in state_type ?
 
5.Can you translate the following to english, please :-
  * inizio a campionare .
  * ci passo una sola volta dopodichè la assegno in LO_DUMMY.
  * rappresentazione in complemento a 2.
 
Finally , I thank you very much . . .
Thanks.
 
oms