关于端口（它是J4）的参考手册是完全错误的，并且在任何情况下，这不是您正在寻找的端口。
I / O分配是指FPGA引脚，它与威廉希尔官方网站
板上的物理连接器不同。
一些FPGA引脚碰巧有像Jxx这样的名称，这纯属巧合。
Jxx通常用于指威廉希尔官方网站
板上的连接器（插孔？）。
听起来系统生成器期望每个音频样本有16位并行输入。
Atlys上的AC'97编解码器是一个定期输出数据帧的串行设备。
您将需要对这些帧进行反序列化（解码），找出哪些帧包含来自该行的音频样本（因为可能有其他帧有其他信息飞来飞去），然后从这些帧中提取样本。
只有这样，才能将16位音频样本传递给DSP设计。
编解码器芯片不会以并行形式输出16位音频样本，因此没有任何物理端口可以执行您要执行的操作。
我不知道如何让System Generator解码AC'97 - 你可能会有更多的运气询问如何在这个william hill官网
的DSP部分做到这一点。
如果您能够创建和集成HDL块，您可以修改Digilent为Atlys提供的示例代码以反序列化AC'97，但如果您不熟悉HDL，这将不是一件小事。
不要忘记，您还需要使用您想要的采样率配置编解码器，并指示它开始对输入进行采样。
编解码器芯片在首次启动时可能根本不会做任何事情。
以上来自于谷歌翻译
以下为原文
The reference manual is
completely wrong with regard to the port (it's J4), and in any case, this isn't the port you're looking for
.
The I/O allocation refers to an FPGA pin, which is different to a physical connector on the board. It's purely a coincidence that some FPGA pins happen to have names like Jxx. Jxx is commonly used to refer to connectors (jacks?) on a circuit board.
It sounds like system generator is expecting a 16-bit parallel input for each audio sample. The AC'97 codec on the Atlys is a serial device that periodically outputs data frames. You will need to deserialise (decode) these frames, figure out which ones contain audio samples from the line in (since there may be other frames with other information flying around), and then extract the samples from these. Only then can you pass the 16-bit audio sample on to your DSP design.
The codec chip simply doesn't output 16-bit audio samples in parallel form, so there isn't any physical port that will do what you're trying to do.
I have no idea how to get System Generator to decode AC'97 - you will probably have more luck asking how to do this in the DSP section of this forum. If you're able to create and integrate HDL blocks, you can modify the example code that Digilent provide with the Atlys to deserialise AC'97, but this will not be a trivial undertaking if you aren't quite familiar with HDL already.
Don't forget that you'll also need to configure the codec with the sample rate you desire and instruct it to start sampling the input. The codec chip may not do anything at all when it's first powered up.
关于端口（它是J4）的参考手册是完全错误的，并且在任何情况下，这不是您正在寻找的端口。
I / O分配是指FPGA引脚，它与威廉希尔官方网站
板上的物理连接器不同。
一些FPGA引脚碰巧有像Jxx这样的名称，这纯属巧合。
Jxx通常用于指威廉希尔官方网站
板上的连接器（插孔？）。
听起来系统生成器期望每个音频样本有16位并行输入。
Atlys上的AC'97编解码器是一个定期输出数据帧的串行设备。
您将需要对这些帧进行反序列化（解码），找出哪些帧包含来自该行的音频样本（因为可能有其他帧有其他信息飞来飞去），然后从这些帧中提取样本。
只有这样，才能将16位音频样本传递给DSP设计。
编解码器芯片不会以并行形式输出16位音频样本，因此没有任何物理端口可以执行您要执行的操作。
我不知道如何让System Generator解码AC'97 - 你可能会有更多的运气询问如何在这个william hill官网
的DSP部分做到这一点。
如果您能够创建和集成HDL块，您可以修改Digilent为Atlys提供的示例代码以反序列化AC'97，但如果您不熟悉HDL，这将不是一件小事。
不要忘记，您还需要使用您想要的采样率配置编解码器，并指示它开始对输入进行采样。
编解码器芯片在首次启动时可能根本不会做任何事情。
以上来自于谷歌翻译
以下为原文
The reference manual is
completely wrong with regard to the port (it's J4), and in any case, this isn't the port you're looking for
.
The I/O allocation refers to an FPGA pin, which is different to a physical connector on the board. It's purely a coincidence that some FPGA pins happen to have names like Jxx. Jxx is commonly used to refer to connectors (jacks?) on a circuit board.
It sounds like system generator is expecting a 16-bit parallel input for each audio sample. The AC'97 codec on the Atlys is a serial device that periodically outputs data frames. You will need to deserialise (decode) these frames, figure out which ones contain audio samples from the line in (since there may be other frames with other information flying around), and then extract the samples from these. Only then can you pass the 16-bit audio sample on to your DSP design.
The codec chip simply doesn't output 16-bit audio samples in parallel form, so there isn't any physical port that will do what you're trying to do.
I have no idea how to get System Generator to decode AC'97 - you will probably have more luck asking how to do this in the DSP section of this forum. If you're able to create and integrate HDL blocks, you can modify the example code that Digilent provide with the Atlys to deserialise AC'97, but this will not be a trivial undertaking if you aren't quite familiar with HDL already.
Don't forget that you'll also need to configure the codec with the sample rate you desire and instruct it to start sampling the input. The codec chip may not do anything at all when it's first powered up.
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