为什么差分时钟与SP6设计一起使用只是为了提高SP6性能？

1.我想知道为什么差分时钟与SP6设计一起使用，只是为了提高SP6性能（或抗噪声）或实现DDR2 / 3类接口的高性能。
请在网上（或只是维基百科）搜索“LVDS”。
2.我可以使用100MHz / 200MHz单端振荡器并使用内部反转为DDR / ethernet / SATA生成具有良好性能的差分时钟......性能会被限制到什么频率？
没有“内部”用户控制的差分信令。
差分信号适用于外部威廉希尔官方网站 板信号，包括FPGA输入和输出。
3. GCLK输入可以用作更好的时钟输出吗？或者如果用作DDR /以太网/ SATA或其他接口的时钟输出，所有FPGA引脚的行为方式相同.....使用单端振荡，r Can
可以生成LVDS输出，我相信是的......确认请？
您可以使用任何IO引脚从FPGA输出时钟，电气特性是统一的。
Spartan-6系列中的所有IO bank均不提供差分输出。
建议您搜索数据表（DS162）。
4.将所有或大部分时钟输入连接到FPGA的Bank1以访问所有PLL / DCM以生成所需频率是一个好主意。
没有进一步的信息，答案是“可能没有”。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索william hill官网 （并搜索网页）以寻找类似的主题。
不要在多个william hill官网 上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付william hill官网 帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

1. i want to know why differential clock is used with SP6 designs, just to improve SP6 performance (or noise immunity) or to achieve high performance regarding the DDR2/3 like interfaces.
 
Please search the web (or just wikipedia) for "LVDS".
 
2. Can i use a 100MHz/200MHz Single Ended Oscillator and use internal inversion to generate differetial clocking for DDR/ethernet/SATA with good performance...will performance be limited upto what frequency ?
 
There is no "internal" user-controlled differential signaling.  Differential signaling applies to external circuit board signals, including FPGA inputs and outputs.
 
3. Can GCLK inputs be used as better clock outputs or not...OR  all FPGA pins behave the same way if used as clock output for DDR/ethernet/SATA or other interfaces.....Using Single Ended oscillato,r Can LVDS output can be generated i believe YES...Confirm Please ??
 
You can use any IO pin for clock output from the FPGA, electrical characteristics are uniform.
Differential outputs are not available for all IO banks in Spartan-6 family.  Suggest you search the datasheet (DS162).
 
4. Is it a good idea idea to connect all or most of the Clock inputs to Bank1 of the FPGA to access all PLL/DCM to generate required frequencies.
 
Without further information, the answer is "probably no".
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

我把不同的信号与用于DDR2 / 3的反向CLK信号混淆.....我想问的是我在一些威廉希尔官方网站 板中看到一些使用带有CLK和CLKn的振荡器（SP605 / 601），有些只有一个CLK
输出（Atlys .. Digilent）......它们对于主题DDR数据速率的重要性在第31页UG382上说“使用单个DCM用于不太关键的应用，两个DCM用于高性能”...同样UG381第50页显示图2
-2具有内部逆变器的BUFG输入“我们可以将这些逆变器用于DDR时钟，还是由MIG / MPMC管理，我们只需要单端时钟。
其次一些设计使用GCLK引脚作为以太网/ SystemACE的时钟输出，但相比之下，DDR2 / 3时钟引脚通常是IO46P和IO46N ......这意味着任何引脚都可以用作DDR接口之外的时钟输出.AM I RIGHT ??
我不想购买昂贵的双输出振荡器（例如SI500或EG2121）我想使用FXO-HC73和LT6905CS并为DDR2，以太网，SATA和其他一些USB IC生成时钟，将大部分连接到Bank1以访问PLL
/ DCM根据要求。
我相信现在我的意图非常清楚..
矩阵



以下为原文

i confused the differntial signalling with inverted CLK signals as used for DDR2/3.....what i wanted to ask was that i saw some in some boards using Oscillators with CLK and CLKn (SP605/601) and some with only one CLK output (Atlys.. Digilent )...what is their significance regarding topics DDR Data Rate on page 31 UG382 which says "use a single DCM for less critical application and two DCM for high performance"...Similarly UG381 page 50 shows  Fig2-2 with BUFG inputs having internal inverters" Can we use these inverters for DDR clocking or that is managed by the MIG/MPMC and we need only single ended clock.
secondly some designs use GCLK pins as clock outputs for Ethernet/SystemACE but in comparison DDR2/3 clock pins are usually IO46P and IO46N...it means any pin could be used as clock output apart from DDR interface..AM I RIGHT  ??
 
I dont want to purchase the costly dual output Oscillator (eg SI500 or EG2121) i want to use rather  FXO-HC73 and LT6905CS and generate clock for DDR2, ethernet, SATA and some other USB IC's connecting most of them to Bank1 to access the PLL/DCM as per requirement.
 
i believe now my intent is very much clear..
 
Matrix
 

如果您的应用程序至关重要，只需使用PLL（不要使用DCM）。
如果实施积极的（操作接近数据表限制）DDR设计，则遵循PLL双输出（CLK和CLK180）的指导来驱动ODDR或OSERDES逻辑。
如果您的设计包含MIG生成的内存控制器，那么让MIG生成后端（内存设备接口）逻辑。
低成本（单端）66MHz硅振荡器作为PLL驱动DDR2-667存储器控制器的输入时钟（非常相当于Atlys设计）应该可靠地工作。
DRAM是一种容忍技术，其他应用可能不太容忍不精确的时基（例如USB，100 / 1000BT，SATA，PCIe）。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索william hill官网 （并搜索网页）以寻找类似的主题。
不要在多个william hill官网 上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付william hill官网 帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

If your application is critical, simply use a PLL (and do not use a DCM).  If implementing an aggressive (operating near datasheet limits) DDR design, then follow the guidance for PLL dual output -- CLK and CLK180 -- to drive the ODDR or OSERDES logic.
 
If your design includes a MIG-generated memory controller, then let MIG generate the back-end (memory device interface) logic.
 
A low-cost (single-ended) 66MHz silicon oscillator as an input clock for a PLL driving DDR2-667 memory controller (very equivalent to Atlys design) should work reliably.  DRAM is a tolerant technology, other applications may be less tolerant of imprecise timebases (e.g. USB, 100/1000BT, SATA, PCIe).
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

非常感谢鲍勃。
我所理解的是，如果我使用MPMC接口DDR2，那么我应该使用PLL来生成DDR时钟，而低成本振荡器将能够令人满意地工作。
我有几个关于这个的问题我可以为MIG和MPMC设计提供相同的引脚排列，如果是，为什么MIG仅提供32位数据总线选项而不是x8或x16数据宽度选项，或者其余的16位可以简单地忽略。
这对我来说会更安全，所以我可以切换b / w MPMC或MIG选项。
你对SATA /以太网接口的说法暗示他们的时钟需要更多关注所以我需要其他精确的时钟选项这些接口我已经在ENTERPOINT Raggedstone设计中看到他们在振荡器之后使用ICS844071进行SATA接口。
同样，其他威廉希尔官方网站 板使用直接与10 / 100base芯片连接的晶体。
我正在使用spartan3AN板上使用的LAN8700.i从插槽中选择了PCIe时钟并使用ICS874001进行了改进。
你是什​​么
在我的建议中建议安全和经济的设计。
对于SSO和其他设计约束，在单个存储体上使用多个时钟输入和输出是否会产生影响。
问候
矩阵



以下为原文

Thanks a lot Bob.
what i have understood is that if i interface DDR2 using MPMC then i should use PLL for DDR clock generation and a low cost oscillator will work satisfactorily. I have a few questions regarding this Could i have same pinouts for the MIG and MPMC design both if YES , Why MIG gives 32 bit data bus option only and not for x8 or x16 data width option or the rest 16 bits could simply be ignored. It will be more safe for me so that i could switch b/w MPMC or MIG options.
 
your saying about SATA/ethernet interfaces implies that their clock needs more care So do i need other precise clocking options for these interfacesas i have seen in an ENTERPOINT Raggedstone design they use ICS844071 after Oscillator for SATA interface. Similarly other boards use a crystal directly connected with the 10/100base chip. i am using LAN8700 used on the spartan3AN board.i have picked  PCIe clock from the slot and is refined using ICS874001. what do you
suggest in my case for a safe and economical design.
 
Does it affect to use multiple clock inputs and outputs on a single bank regarding SSO and other design constraints.
regards
 
Matrix