VC707板中的引脚分配错误该怎么办？

今天，VC707用户指南中仍然存在错误，即使文档已在上一条消息之后更新。
http://www.xilinx.com/support/documentation/boards_and_kits/vc707/ug885_VC707_Eval_Bd.pdf
第81页
NET USB_UART_RX LOC = AU36 |
IOSTANDARD = LVCMOS18;
#Bank 13 VCCO - VCC1V8_FPGA - IO_L8N_T1_13
NET USB_UART_RTS LOC = AT32 |
IOSTANDARD = LVCMOS18;
#Bank 13 VCCO - VCC1V8_FPGA - IO_L9P_T1_DQS_13
NET USB_UART_TX LOC = AU33 |
IOSTANDARD = LVCMOS18;
#Bank 13 VCCO - VCC1V8_FPGA - IO_L9N_T1_DQS_13
NET USB_UART_CTS LOC = AR34 |
IOSTANDARD = LVCMOS18;
#Bank 13 VCCO - VCC1V8_FPGA - IO_L10P_T1_13
它应该是：
NET USB_UART_RX LOC = AU33 |
IOSTANDARD = LVCMOS18;
#Bank 13 VCCO - VCC1V8_FPGA - IO_L8N_T1_13
NET USB_UART_RTS LOC = AT32 |
IOSTANDARD = LVCMOS18;
#Bank 13 VCCO - VCC1V8_FPGA - IO_L9P_T1_DQS_13
NET USB_UART_TX LOC = AU36 |
IOSTANDARD = LVCMOS18;
#Bank 13 VCCO - VCC1V8_FPGA - IO_L9N_T1_DQS_13
NET USB_UART_CTS LOC = AR34 |
IOSTANDARD = LVCMOS18;
#Bank 13 VCCO - VCC1V8_FPGA - IO_L10P_T1_13