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[问答]

怎样去编写74LS00芯片的代码程序呢

怎样去编写74LS00芯片的代码程序呢?
怎样去编写74LS04芯片的代码程序呢?

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李冬茗

2021-11-5 15:38:00
  相关部分代码:74LS00芯片
  module my74LS00(a,b,out1);
  input a,b; //SW[0]/SW[1]==AB28/AC28
  output out1; //LEDR[0]/LEDR[1]==G19/F19
  assign out1 =~(a&&b);
  //assign out1 =a;
  //assign out2 =b;
  endmodule
  74LS04芯片
  module my74LS04(a,out1);
  input a; //SW[0]/SW[1]==AB28/AC28
  output out1; //LEDR[0]/LEDR[1]==G19/F19
  assign out1 =~a;
  //assign out1 =a;
  //assign out2 =b;
  endmodule
  与门:
  module andgate(a,b,F);
  input a;
  input b;
  output F;
  wire Lin1;
  my74LS00 u0(a,b,Lin1);
  my74LS04 u1(Lin1,F);
  endmodule
  testbench:
  initial
  begin
  a=0;b=0;
  #100 a=1;b=0;
  #100 a=0;b=1;
  #100 a=1;b=1;
  $display(“Running testbench”);
  end
  或门:
  module orgate(a,b,F);
  input a,b; //SW[0]/SW[1]==AB28/AC28
  output F; //LEDR[0]/LEDR[1]==G19/F19
  wire Lin1;
  wire Lin2;
  //my74LS00 u0(a,1,Lin1);
  my74LS04 u0(a,Lin1);
  my74LS00 u1(b,1,Lin2);
  my74LS00 u2(Lin1,Lin2,F);
  //assign out1 =a;
  //assign out2 =b;
  endmodule
  testbench:
  initial
  begin
  a=0;b=0;
  #100 a=1;b=0;
  #100 a=0;b=1;
  #100 a=1;b=1;
  $display(“Running testbench”);
  end
  与或门:
  module andorgate(a,b,c,d,F);
  input a;
  input b;
  input c;
  input d;
  wire Lin1;
  wire Lin2;
  output F;
  my74LS00 u0(a,b,Lin1);
  my74LS00 u1(c,d,Lin2);
  my74LS00 u2(Lin1,Lin2,F);
  endmodule
  testbench:
  initial
  begin
  a=0;b=0;c=0;d=0;
  #100 a=0;b=0;c=0;d=1;
  #100 a=0;b=0;c=1;d=0;
  #100 a=0;b=1;c=0;d=0;
  #100 a=1;b=0;c=0;d=0;
  #100 a=0;b=0;c=1;d=1;
  #100 a=0;b=1;c=0;d=1;
  #100 a=1;b=0;c=0;d=1;
  #100 a=0;b=1;c=1;d=0;
  #100 a=1;b=0;c=1;d=0;
  #100 a=1;b=1;c=0;d=0;
  #100 a=1;b=1;c=1;d=0;
  #100 a=1;b=1;c=0;d=1;
  #100 a=1;b=0;c=1;d=1;
  #100 a=0;b=1;c=1;d=1;
  #100 a=1;b=1;c=1;d=1;
  $display(“Running testbench”);
  end
  异或门:
  module difforgate(a,b,F);
  input a;
  input b;
  output F;
  wire Lin1;
  wire Lin2;
  wire Lin3;
  wire Lin4;
  my74LS04 u0(a,Lin1);
  my74LS04 u1(b,Lin2);
  my74LS00 u2(Lin1,b,Lin3);
  my74LS00 u3(a,Lin2,Lin4);
  my74LS00 u4(Lin3,Lin4,F);
  endmodule
  testbench:
  initial
  begin
  a=0;b=0;
  #100 a=1;b=0;
  #100 a=0;b=1;
  #100 a=1;b=1;
  $display(“Running testbench”);
  end
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