Okmx6ul自制底板音频驱动DMA不能中断响应是为什么？

底板音频模块原理和开发板一样，同样的核心板在开发板播放音频正常，在我的底板就不行，调试发现DMA pending后没产生DMA中断，数据都到不了8960。
想问下底板的什么变动有可能导致音频驱动出现这种问题

范云力

2022-1-7 11:12:51

估计wm8960没有正常工作，正常情况下播放音频文件的时候mclk会有输出的，可以看一下wm8960的驱动有没有注册成功，还有i2c接的对不对，是通过i2c2来配置wm8960的

陈衍暖

2022-1-7 11:13:12

soc 是主，8960是从

张杰

2022-1-7 11:13:25

[ 32.269233] [531] snd_soc_write:2296: wm8960 1-001a: write 7 = 42
这是我的输出

R7 (07h)       8       ALRSWAP                0                Left/Right ADC Channel Swap                               Audio Inte**ce
Audio                                                                1 = Swap left and right ADC data in audio                   Control

Inte**ce                                                          inte**ce

                                                                        0 = Output left and right data as normal

                  7       BCLKINV                0                BCLK invert bit (for master and slave modes)                Audio Inte**ce
                                                                        0 = BCLK not inverted                                        Control

                                                                        1 = BCLK inverted

                  6       MS                      0                Master / Slave Mode Control                               Audio Inte**ce
                                                                        0 = Enable slave mode                                        Control

                                                                        1 = Enable master mode

                  5       DLRSWAP                0                Left/Right DAC Channel Swap                               Audio Inte**ce
                                                                        0 = Output left and right data as normal                   Control

                                                                        1 = Swap left and right DAC data in audio
                                                                        inte**ce

                                                                                          2
                  4       LRP                   0                Right, left and I S modes – LRCLK polarity                Audio Inte**ce
                                                                        0 = normal LRCLK polarity                                  Control

                                                                        1 = invert LRCLK polarity

                                                                        DSP Mode – mode A/B select

                                                                        0 = MSB is available on 2nd BCLK rising edge
                                                                        after LRC rising edge (mode A)

                                                                        1 = MSB is available on 1st BCLK rising edge
                                                                        after LRC rising edge (mode B)

                  3:2    WL[1:0]                10             Audio Data Word Length                                     Audio Inte**ce
                                                                        00 = 16 bits                                                 Control

                                                                        01 = 20 bits

                                                                        10 = 24 bits

                                                                        11 = 32 bits (see Note)

[ 32.269233] [531] snd_soc_write:2296: wm8960 1-001a: write 7 = 42
这是我的输出

R7 (07h)       8       ALRSWAP                0                Left/Right ADC Channel Swap                               Audio Inte**ce
Audio                                                                1 = Swap left and right ADC data in audio                   Control

Inte**ce                                                          inte**ce

                                                                        0 = Output left and right data as normal

                  7       BCLKINV                0                BCLK invert bit (for master and slave modes)                Audio Inte**ce
                                                                        0 = BCLK not inverted                                        Control

                                                                        1 = BCLK inverted

                  6       MS                      0                Master / Slave Mode Control                               Audio Inte**ce
                                                                        0 = Enable slave mode                                        Control

                                                                        1 = Enable master mode

                  5       DLRSWAP                0                Left/Right DAC Channel Swap                               Audio Inte**ce
                                                                        0 = Output left and right data as normal                   Control

                                                                        1 = Swap left and right DAC data in audio
                                                                        inte**ce

                                                                                          2
                  4       LRP                   0                Right, left and I S modes – LRCLK polarity                Audio Inte**ce
                                                                        0 = normal LRCLK polarity                                  Control

                                                                        1 = invert LRCLK polarity

                                                                        DSP Mode – mode A/B select

                                                                        0 = MSB is available on 2nd BCLK rising edge
                                                                        after LRC rising edge (mode A)

                                                                        1 = MSB is available on 1st BCLK rising edge
                                                                        after LRC rising edge (mode B)

                  3:2    WL[1:0]                10             Audio Data Word Length                                     Audio Inte**ce
                                                                        00 = 16 bits                                                 Control

                                                                        01 = 20 bits

                                                                        10 = 24 bits

                                                                        11 = 32 bits (see Note)

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范云力

陈衍暖

张杰

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