仿真VCD文件系统任务的问题

我看夏 宇闻老师的书第97页有个例子，我打算做一下，可是不成功

代码：

`timescale 1 ns/ 1 ps
module LAMP_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg rst_n;
// wires
wire led;

// assign statements (if any)
LAMP i1 (
// port map - connection between master ports and signals/registers
.clk(clk),
.led(led),
.rst_n(rst_n)
);

module M;
initial
$display("Displaying in %m");
endmodule

module top;
M m1();
M m2();
M m3();
endmodule

module chufa;
initial
$dumpfile("myfile.dmp");
initial
$dumpvars;
initial
$dumpvars(1,top); //?
initial
$dumpvars(2,top.m1);
initial
$dumpvars(0,top.m1);
initial begin
$dumpon;
#100 $dumpoff;
$dumplimit(2000);
end
initial
$dumpall;
endmodule

endmodule

提示出错

$dumpvars(2,top.m1);这句话有问题。
请高手指教，谢谢