reg sda_internal;
always @(posedge clk or posedge rst) begin
if (rst) begin
sda_internal <= 1'b0; // Reset the internal signal
end else begin
sda_internal <=(sda_out_en==1)?sda_out:sda;
end
end
assign sda=sda_internal;
end
end
reg sda_internal;
always @(posedge clk or posedge rst) begin
if (rst) begin
sda_internal <= 1'b0; // Reset the internal signal
end else begin
sda_internal <=(sda_out_en==1)?sda_out:sda;
end
end
assign sda=sda_internal;
end
end