自己写了一个verilog程序，例化了ISE里面自带的Clock IP核，然后用定时器延时，实现LED的闪烁，就这么一个比较简单的程序，综合的时候却总是报错，错误如下：
ERROR:Pack:2531 - The dual data rate register "gen_outclk_oddr[2].clkout_oddr"
failed to join the "OLOGIC2" component as required. The output signal for
register symbol gen_outclk_oddr[2].clkout_oddr requires general rou
ting to
fabric, but the register can only be routed to ILOGIC, IODELAY, and IOB.
请高手指教！谢谢！
举报
