我在PR设计方面遇到了麻烦，所以我试图退后一步并在相同的条件下实现它，但没有PR约束。
我正在尝试使用相同的工具（PlanAhead）来保持尽可能多的变量。
我有一个.ngc，.edf和.ucf，我试图使用，但最初我不能创建仅使用静态逻辑的设计运行。
但是，通过将.edf标记为分区，然后将其作为分区删除，我有一些运气。
在此之后，我可以选择使用仅静态逻辑创建设计运行。
我创建了位文件，它似乎按照需要工作。
那么PlanAhead中允许的功能是什么，完成它的正确方法是什么？
以上来自于谷歌翻译
以下为原文
I had trouble with a PR design, so I'm trying to take a step back and implement it under the same condi
tions, but without the PR constraints. I'm trying to use the same tool (PlanAhead) to keep as many variables as possible the same.
I have an .ngc , .edf and .ucf that I am trying to use, but initially I cannot create a design run with static logic only.
However, I have had some luck, by marking the .edf as a partition, then removing it as a partiton. After this I have the option of creating a design run with static only logic. I created the bit file and it seems to work as desired. So is this functionality allowed in PlanAhead and what is the proper way to accomplish it?
举报
