x继Xilinx的加密ip能还原rtl后，Altera的加密IP也可还原了。
比如altera12.1ipalteraviterbilibauk_vit_hyb_sur_atl_ent.vhd是这样的
Offset 0 1 2 3 4 5 6 7 8 9 A B C D E F
00000000 8B 13 9C 2F 06 00 04 00 22 BE 09 67 A1 12 4A 70 ?? "?g?Jp
00000010 98 DE 6B 56 B7 65 D4 C7 42 92 E4 19 7F 29 7D 2D 樲kV積郧B掍 )}-
00000020 51 18 4C 6F 59 8B B4 0C 99 B7 E6 61 19 19 84 66 Q LoY嫶 櫡鎍 刦
00000030 DC A2 48 05 56 6E 34 91 8A 77 11 C3 8A 97 AF 9C 堍H Vn4憡w 脢棷?
00000040 30 EC 46 97 DE 82 D3 33 08 69 BE C3 FD 67 CD B2 0霧椶傆3 i久齡筒
可以还原成
-------------------------------------------------------------------------
-------------------------------------------------------------------------
--
-- Revision Control Information
--
-- $Workfile: auk_vit_hyb_sur_atl_ent.vhd $
-- $Archive: Y:/IP_PVCS/archives/Viterbi/Units/hybrid/atlantic/auk_vit_hyb_sur_atl_ent.vhd-arc $
--
-- $RCSfile: auk_vit_hyb_sur_atl_ent.vhd,v $
-- $Source: /disk2/cvs/data/Projects/Viterbi/Units/hybrid/atlantic/Attic/auk_vit_hyb_sur_atl_ent.vhd,v $
--
-- $Revision: #1 $
-- $Date: 2012/08/12 $
-- Check in by : $Author: swbranch $
-- Author : Alejandro Diaz-Manero
--
-- Project : Viterbi
--
-- Description :
--
-- ALTERA Confidential and Proprietary
-- Copyright 2000 (c) Altera Corporation
-- All rights reserved
--
-------------------------------------------------------------------------
-------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
Entity auk_vit_hyb_sur_atl is
Generic (
L : NATURAL := 7;
ACS_units : NATURAL := 4
);
Port (
clk, reset : in Std_Logic;
survtop, survbot : in Std_Logic_Vector(ACS_units downto 1);
survive : out Std_Logic_Vector(2**(L-1) downto 1)
);
end entity auk_vit_hyb_sur_atl;
x继Xilinx的加密ip能还原rtl后，Altera的加密IP也可还原了。
比如altera12.1ipalteraviterbilibauk_vit_hyb_sur_atl_ent.vhd是这样的
Offset 0 1 2 3 4 5 6 7 8 9 A B C D E F
00000000 8B 13 9C 2F 06 00 04 00 22 BE 09 67 A1 12 4A 70 ?? "?g?Jp
00000010 98 DE 6B 56 B7 65 D4 C7 42 92 E4 19 7F 29 7D 2D 樲kV積郧B掍 )}-
00000020 51 18 4C 6F 59 8B B4 0C 99 B7 E6 61 19 19 84 66 Q LoY嫶 櫡鎍 刦
00000030 DC A2 48 05 56 6E 34 91 8A 77 11 C3 8A 97 AF 9C 堍H Vn4憡w 脢棷?
00000040 30 EC 46 97 DE 82 D3 33 08 69 BE C3 FD 67 CD B2 0霧椶傆3 i久齡筒
可以还原成
-------------------------------------------------------------------------
-------------------------------------------------------------------------
--
-- Revision Control Information
--
-- $Workfile: auk_vit_hyb_sur_atl_ent.vhd $
-- $Archive: Y:/IP_PVCS/archives/Viterbi/Units/hybrid/atlantic/auk_vit_hyb_sur_atl_ent.vhd-arc $
--
-- $RCSfile: auk_vit_hyb_sur_atl_ent.vhd,v $
-- $Source: /disk2/cvs/data/Projects/Viterbi/Units/hybrid/atlantic/Attic/auk_vit_hyb_sur_atl_ent.vhd,v $
--
-- $Revision: #1 $
-- $Date: 2012/08/12 $
-- Check in by : $Author: swbranch $
-- Author : Alejandro Diaz-Manero
--
-- Project : Viterbi
--
-- Description :
--
-- ALTERA Confidential and Proprietary
-- Copyright 2000 (c) Altera Corporation
-- All rights reserved
--
-------------------------------------------------------------------------
-------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
Entity auk_vit_hyb_sur_atl is
Generic (
L : NATURAL := 7;
ACS_units : NATURAL := 4
);
Port (
clk, reset : in Std_Logic;
survtop, survbot : in Std_Logic_Vector(ACS_units downto 1);
survive : out Std_Logic_Vector(2**(L-1) downto 1)
);
end entity auk_vit_hyb_sur_atl;
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