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74HC164 pdf datasheet
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大小:134 |
2008-08-06
欲望都市
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MM54HC164/MM74HC164
8-Bit Serial-in/Parallel-out Shift Register
General Description
The MM54HC164/MM74HC164 utilizes advanced silicongate
CMOS technology. It has the high noise immunity and
low consumption of standard CMOS integrated circuits. It
also offers speeds comparable to low power Schottky devices.
This 8-Bit shift register has gated serial inputs and CLEAR.
Each register bit is a D-type master/slave flip flop. Inputs A
& B permit complete control over the incoming data. A low
at either or both inputs inhibits entry of new data and resets
the first flip flop to the low level at the next clock pulse. A
high level on one input enables the other input which will
then determine the state of the first flip flop. Data at the
serial inputs may be changed while the clock is high or low,
but only information meeting the setup and hold time requirements
will be entered. Data is serially shifted in and out
of the 8-Bit register during the positive going transition of
the clock pulse. Clear is independent of the clock and accomplished
by a low level at the CLEAR input.
The 54HC/74HC logic family is functionally as well as pinout
compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static discharge
by internal diode clamps to VCC and ground.
8-Bit Serial-in/Parallel-out Shift Register
General Description
The MM54HC164/MM74HC164 utilizes advanced silicongate
CMOS technology. It has the high noise immunity and
low consumption of standard CMOS integrated circuits. It
also offers speeds comparable to low power Schottky devices.
This 8-Bit shift register has gated serial inputs and CLEAR.
Each register bit is a D-type master/slave flip flop. Inputs A
& B permit complete control over the incoming data. A low
at either or both inputs inhibits entry of new data and resets
the first flip flop to the low level at the next clock pulse. A
high level on one input enables the other input which will
then determine the state of the first flip flop. Data at the
serial inputs may be changed while the clock is high or low,
but only information meeting the setup and hold time requirements
will be entered. Data is serially shifted in and out
of the 8-Bit register during the positive going transition of
the clock pulse. Clear is independent of the clock and accomplished
by a low level at the CLEAR input.
The 54HC/74HC logic family is functionally as well as pinout
compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static discharge
by internal diode clamps to VCC and ground.
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