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74LS194A pdf datasheet
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2008-08-06
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54LS194A/DM74LS194A 4-Bit
Bidirectional Universal Shift Register
General Description
This bidirectional shift register is designed to incorporate
virtually all of the features a system designer may want in a
shift register; they feature parallel inputs, parallel outputs,
right-shift and left-shift serial inputs, operating-mode-control
inputs, and a direct overriding clear line. The register has
four distinct modes of operation, namely:
Parallel (broadside) load
Shift right (in the direction QA toward QD)
Shift left (in the direction QD toward QA)
Inhibit clock (do nothing)
Synchronous parallel loading is accomplished by applying
the four bits of data and taking both mode control inputs, S0
and S1, high. The data is loaded into the associated flipflops
and appear at the outputs after the positive transition
of the clock input. During loading, serial data flow is inhibited.
Shift right is accomplished synchronously with the rising
edge of the clock pulse when S0 is high and S1 is low.
Serial data for this mode is entered at the shift-right data
input. When S0 is low and S1 is high, data shifts left synchronously
and new data is entered at the shift-left serial
input.
Clocking of the flip-flop is inhibited when both mode control
inputs are low.
Features
Y Parallel inputs and outputs
Y Four operating modes:
Synchronous parallel load
Right shift
Left shift
Do nothing
Y Positive edge-triggered cl
Bidirectional Universal Shift Register
General Description
This bidirectional shift register is designed to incorporate
virtually all of the features a system designer may want in a
shift register; they feature parallel inputs, parallel outputs,
right-shift and left-shift serial inputs, operating-mode-control
inputs, and a direct overriding clear line. The register has
four distinct modes of operation, namely:
Parallel (broadside) load
Shift right (in the direction QA toward QD)
Shift left (in the direction QD toward QA)
Inhibit clock (do nothing)
Synchronous parallel loading is accomplished by applying
the four bits of data and taking both mode control inputs, S0
and S1, high. The data is loaded into the associated flipflops
and appear at the outputs after the positive transition
of the clock input. During loading, serial data flow is inhibited.
Shift right is accomplished synchronously with the rising
edge of the clock pulse when S0 is high and S1 is low.
Serial data for this mode is entered at the shift-right data
input. When S0 is low and S1 is high, data shifts left synchronously
and new data is entered at the shift-left serial
input.
Clocking of the flip-flop is inhibited when both mode control
inputs are low.
Features
Y Parallel inputs and outputs
Y Four operating modes:
Synchronous parallel load
Right shift
Left shift
Do nothing
Y Positive edge-triggered cl
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