划分和时延驱动的动态可重构FPGA在线布局算法

可编程逻辑芯片特别是FPGA的快速发展，使得新的芯片能够根据具体应用动态地调整结构以获得更好的性能，这类芯片称为动态可重构FPGA芯片（DRFPGA）。然而，使用这类芯片构建的可重构系统在实际应用前还有许多问题需要解决。本文提出一个基于划分和时延驱动的在线布局算法，来解决动态可重构FPGA芯片的布局问题。实验结果表明，我们的布局算法与传统的布局算法相比，在时延上平均减少27%，在线长上平均减少34%，在运行时间上平均减少42%。
关键词 划分布局；时延驱动；动态可重构FPGA；模型

Abstract The advances in the programmable logic devices especially Field-Programmable Gate Arrays (FPGA) have led to new architectures where the hardware can be dynamically adapted to the application to gain better performance. This kind of FPGA is called Dynamically Reconfigurable FPGA (DRFPGA). However, there are still many challenging problems to be solved before any practical reconfigurable system is built. In this paper, we present a partitioning-based timing-driven online placement for DRFPGAs. Experimental results show that our placement scheme achieves on average a total decrease of 27% in delay, 34% in wire-length and 42% in runtime, compared with the traditional placement methods.
Key words Partitioning-based Placement; Timing-driven; Dynamic Reconfigurable FPGA; Model