基于FPGA的高速同步HDLC通信控制器设计

高级数据链路控制HDLC协议是一种面向比特的链路层协议，具有同步传输数据、冗余度低等特点，是在通信领域中应用最广泛的链路层协议之一。提出实现HDLC通信协议的主要模块——CRC校验模块及‘0’比特插入模块的FPGA实现方法。CRC校验模块采用状态机设计方法，而‘0’比特插入模块是利用FIFO实现，为HDLC通信控制器的设计提供新的思路。该方法已在Spartan3s400开发板上实现，并能正确传输。

Abstract:

 High-level Data Link Control（HDLC）protocol is a bit-oriented synchronous data link layer protocol，it is synchronous and its low degree of redundancy，it is one of the most extensively applied data link control protocols. In this paper，CRC verification module and ‘0’ insert module based on FPGA as the most important function module in the HDLC protocol are introduced. CRC verification module used state machine and ‘0’ insert module used FIFO as the primary module，which offered some new ideas of the design of HDLC protocol controller. The method was realized and correctly transmitted on Spartan3s400 DevKit.