The ADP1754/ADP1755 are low dropout (LDO) CMOS linear regulators that operate from 1.6 V to 3.6 V and provide up to 1.2 A of output current. These low VIN/VOUT LDOs are ideal for regulation of nanometer FPGA geometries operating from 2.5 V down to 1.8 V I/O rails, and for powering core voltages down to 0.75 V. Using an advanced proprietary architecture, the ADP1754/ ADP1755 provide high power supply rejection ratio (PSRR) and low noise, and achieve excellent line and load transient response with only a small 4.7 µF ceramic output capacitor. The ADP1754 is available in seven fixed output voltage options. The ADP1755 is the adjustable version, which allows output voltages that range from 0.75 V to 3.3 V via an external divider. The ADP1754/ADP1755 allow an external soft start capacitor to be connected to program the startup. A digital power-good output allows power system monitors to check the health of the output voltage. The ADP1754/ADP1755 are available in a 16-lead, 4 mm × 4 mm LFCSP, making them not only very compact solutions, but also providing excellent thermal performance for applications that require up to 1.2 A of output current in a small, low profile footprint.
声明:本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人,不代表电子发烧友网立场。文章及其配图仅供工程师学习之用,如有内容侵权或者其他违规问题,请联系本站处理。 举报投诉
全部0条评论
快来发表一下你的评论吧 !