DS2151, DS2153 Interfacing to
通信设计应用
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描述
Abstract: Application Note 312 provides a logical diagram of the interface of the Dallas Semiconductor/Maxim DS2151 T1 single chip transceiver (SCT) and DS2153 E1 SCT to the Siemens PEB20320.
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Notes:
- Both the DS2151 and the DS2153 are set up with both the receive and transmit elastic stores disabled.
- Shown is a "looped-timed" application.
- The RSYNC pin is programmed to be an output; the TSYNC pin is programmed to be an input.
- RCHBLK is programmed to be set high except in the last channel of each frame.
- Timing between the devices is shown below:
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