Vivado常见Warning问题解决方法

目录

1、[Synth 8-2611] redeclaration of ansi port XXX is not allowed

2、[Constraints 18-619] A clock with name 'InClk' already exists

3、 [Synth 8-2611] redeclaration of ansi port InClk is not allowed

4、 [Vivado 12-1017] Problems encountered:

5、 [Constraints 18-5210] No constraint will be written out.

6、[Common 17-1548] Command failed: can't read "output_ports": no such variable

7、[filemgmt 20-2001] Source scanning failed (terminated by user) while processing fileset "sources_1" due to unrecoverable syntax error or design hierarchy issues. Recovering last known analysis of the source files.

8、[Synth 8-1849] concatenation with unsized literal; will interpret as 32 bits

9、[Constraints 18-549] Could not create 'SLEW' constraint because cell 'OBUFDS_inst' is not directly connected to top level port. 'SLEW' is ignored by Vivado but preserved inside the database.

1、[Synth 8-2611] redeclaration of ansi port XXX is not allowed

程序中重复声明输出端口信号

2、[Constraints 18-619] A clock with name 'InClk' already exists

描述：

在约束文件XDC（SCOPED_TO_REF、SCOPED_TO_CELLS）中使用“create_clock -name”约束时，在打开综合设计或实现设计时，或者在综合或实现期间，可以观察到以下警告。

[Constraints 18-619] A clock with name 'InClk' already exists overwriting the previous clock with the same name. ["E:/Vivado_Project/DispTimGen/DispTimGen.srcs/constrs_1/new/DispTimGenTiming.xdc":1]

解决方案：

如果时钟约束已存在于 IP XDC 中，则无需在顶级 xdc 中写入约束。

clk_wiz_0.xdc文件中如下已经约束InClk；

当设计中有多个作用域单元/引用的实例时会显示此警告，因此多次读取相同的“create_clock -name”约束。

如警告消息中所示，仅最后一个读取保留，所有其他读取都丢失。

推荐的解决方案是从 create_clock 命令中删除 -name 选项。

如果未使用 -name 选项，系统会根据网络名/位置创建唯一名称。

3、 [Synth 8-2611] redeclaration of ansi port InClk is not allowed

输入端口不需要申明wire型

4、 [Vivado 12-1017] Problems encountered:

[Vivado 12-1017] Problems encountered: Failed to delete one or more files in run directory E:/Vivado_Project/DispTimGen/DispTimGen.runs/synth_1

描述：保存Project文件夹为可读模式

解决方案：设置保存Project文件权限，设置为读写模式

5、 [Constraints 18-5210] No constraint will be written out.

解决方案：Vivado 中的一个已知错误，将在 2020.1 中修复（可以忽略）

6、[Common 17-1548] Command failed: can't read "output_ports": no such variable

描述：set_input_delay时，端口命名错误

解决方案：set_input_delay端口命名时，将< >去掉

7、[filemgmt 20-2001] Source scanning failed (terminated by user) while processing fileset "sources_1" due to unrecoverable syntax error or design hierarchy issues. Recovering last known analysis of the source files.

重启软件可解决

8、[Synth 8-1849] concatenation with unsized literal; will interpret as 32 bits

问题在了 {} 里面的 “0” 了，原来在拼接符中的0，如果不指定其位数，则软件会将其默认为32bit，如果这个0不在高位，那么在进行赋值的时候就会形成了将一个很多位的数据赋值给了2bit的BramRst。

9、[Constraints 18-549] Could not create 'SLEW' constraint because cell 'OBUFDS_inst' is not directly connected to top level port. 'SLEW' is ignored by Vivado but preserved inside the database.

约束 [18-549] 无法创建“SLEW”约束，因为单元“OBUFDS_inst”未直接连接到顶级端口。Vivado 会忽略“SLEW”，但会保留在数据库中。

注意：INBUFDS与OBUFDS这类源语言是必须要有硬件连接的In或Out接口！
 

　　审核编辑：汤梓红