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DS90CR485,pdf datasheet (133MH
消耗积分:3 |
格式:rar |
大小:556 |
2009-10-14
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The DS90CR485 serializes the 24 LVCMOS/LVTTL double
edge inputs (48 bits data latched in per clock cycle) onto 8
Low Voltage Differential Signaling (LVDS) streams. A phaselocked
transmit clock is also in parallel with the data streams
over a 9th LVDS link. The reduction of the wide TTL bus to a
few LVDS lines reduces cable and connector size and cost.
The double edge input strobes data on both the rising and
falling edges of the clock. This minimizes the pin count
required and simplifies PCB routing between the host chip
and the serializer.
edge inputs (48 bits data latched in per clock cycle) onto 8
Low Voltage Differential Signaling (LVDS) streams. A phaselocked
transmit clock is also in parallel with the data streams
over a 9th LVDS link. The reduction of the wide TTL bus to a
few LVDS lines reduces cable and connector size and cost.
The double edge input strobes data on both the rising and
falling edges of the clock. This minimizes the pin count
required and simplifies PCB routing between the host chip
and the serializer.
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