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74LS173 pdf datasheet
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2008-08-06
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54LS173/DM74LS173A
TRI-STATEÉ 4-Bit D-Type Register
General Description
This four-bit register contains D-type flip-flops with totempole
TRI-STATEÉ outputs, capable of driving highly capacitive
or low-impedance loads. The high-impedance state and
increased high-logic-level drive provide these flip-flops with
the capability of driving the bus lines in a bus-organized system
without need for interface or pull-up components.
Gated enable inputs are provided for controlling the entry of
data into the flip-flops. When both data-enable inputs are
low, data at the D inputs are loaded into their respective flipflops
on the next positive transition of the buffered clock
input. Gate output control inputs are also provided. When
both are low, the normal logic states of the four outputs are
available for driving the loads or bus lines. The outputs are
disabled independently from the level of the clock by a high
logic level at either output control input. The outputs then
present a high impedance and neither load nor drive the bus
line. Detailed operation is given in the truth table.
To minimize the possibility that two outputs will attempt to
take a common bus to opposite logic levels, the output control
circuitry is designed so that the average output disable
times are shorter than the average output enable times.
Features
Y TRI-STATE outputs interface directly with system bus
Y Gated output control lines for enabling or disabling the
outputs
Y Fully independent clock eliminates restrictions for operating
in one of two modes:
Parallel load
Do nothing (hold)
Y For application as bus buffer registers
TRI-STATEÉ 4-Bit D-Type Register
General Description
This four-bit register contains D-type flip-flops with totempole
TRI-STATEÉ outputs, capable of driving highly capacitive
or low-impedance loads. The high-impedance state and
increased high-logic-level drive provide these flip-flops with
the capability of driving the bus lines in a bus-organized system
without need for interface or pull-up components.
Gated enable inputs are provided for controlling the entry of
data into the flip-flops. When both data-enable inputs are
low, data at the D inputs are loaded into their respective flipflops
on the next positive transition of the buffered clock
input. Gate output control inputs are also provided. When
both are low, the normal logic states of the four outputs are
available for driving the loads or bus lines. The outputs are
disabled independently from the level of the clock by a high
logic level at either output control input. The outputs then
present a high impedance and neither load nor drive the bus
line. Detailed operation is given in the truth table.
To minimize the possibility that two outputs will attempt to
take a common bus to opposite logic levels, the output control
circuitry is designed so that the average output disable
times are shorter than the average output enable times.
Features
Y TRI-STATE outputs interface directly with system bus
Y Gated output control lines for enabling or disabling the
outputs
Y Fully independent clock eliminates restrictions for operating
in one of two modes:
Parallel load
Do nothing (hold)
Y For application as bus buffer registers
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