您好!
使用DLP9500UV的DLP系统框图如下图所示:
输入信号为
Four 16-Bit, Low-Voltage Differential Signaling (LVDS), Double Data Rate (DDR) Input Data Buses
Serial Communication and configuration interface
具体请参考Page23功能框图
http://www.ti.com/lit/ds/symlink/dlpc410.pdf
您好!
使用DLP9500UV的DLP系统框图如下图所示:
输入信号为
Four 16-Bit, Low-Voltage Differential Signaling (LVDS), Double Data Rate (DDR) Input Data Buses
Serial Communication and configuration interface
具体请参考Page23功能框图
http://www.ti.com/lit/ds/symlink/dlpc410.pdf
举报