引用: dlmn 发表于 2018-6-22 04:16
不是让DSP/M3直接访问PCIe空间。
是让PCIe EP(FPGA)通过PCIe将视频YUV帧传到A8/M3VPSS shared region,我忘了是SR0,1还是几了。这样M3VPSS拿YUV帧就可以从shared region拿了,就不用A8再copy过去了,节省DDR带宽。
你好,
从下面的信息看,应该是可以的,从0x8000000开始的2GB空间都可以映射为inbound memory。
http://processors.wiki.ti.com/index.php/TI81XX_PSP_PCI_Express_Root_Complex_Driver_User_Guide#System_Resources
Inbound Memory
This memory is used to map TI81XX RAM so as to enable external masters (EP) to have access.
- Generally this should be the complete RAM available to kernel. Currently whole 2GB DDR space starting from 0x80000000 is provided for inbound memory access.
You can change this by updating ti81xx_pcie_resources data in arch/arm/mach-omap2/devices.c for "pcie-inbound0" resource:
[ /* Inbound memory window */ .name = "pcie-inbound0", .start = PHYS_OFFSET, .end = PHYS_OFFSET +
SZ_2G - 1, .flags = IORESOURCE_MEM, ],
引用: dlmn 发表于 2018-6-22 04:16
不是让DSP/M3直接访问PCIe空间。
是让PCIe EP(FPGA)通过PCIe将视频YUV帧传到A8/M3VPSS shared region,我忘了是SR0,1还是几了。这样M3VPSS拿YUV帧就可以从shared region拿了,就不用A8再copy过去了,节省DDR带宽。
你好,
从下面的信息看,应该是可以的,从0x8000000开始的2GB空间都可以映射为inbound memory。
http://processors.wiki.ti.com/index.php/TI81XX_PSP_PCI_Express_Root_Complex_Driver_User_Guide#System_Resources
Inbound Memory
This memory is used to map TI81XX RAM so as to enable external masters (EP) to have access.
- Generally this should be the complete RAM available to kernel. Currently whole 2GB DDR space starting from 0x80000000 is provided for inbound memory access.
You can change this by updating ti81xx_pcie_resources data in arch/arm/mach-omap2/devices.c for "pcie-inbound0" resource:
[ /* Inbound memory window */ .name = "pcie-inbound0", .start = PHYS_OFFSET, .end = PHYS_OFFSET +
SZ_2G - 1, .flags = IORESOURCE_MEM, ],
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