XADC和AXI4Lite接口：定制AXI引脚

查看此XAPPshttps：//www.xilinx.com/support/documentation/application_notes/xapp1183-zynq-xadc-axi.pdf
谢谢和RegardsBalkrishan -----------------------------------------------
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以下为原文

check this XAPPs
https://www.xilinx.com/support/documentation/application_notes/xapp1183-zynq-xadc-axi.pdfThanks and Regards
Balkrishan
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Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.View solution in original post

查看此XAPPshttps：//www.xilinx.com/support/documentation/application_notes/xapp1183-zynq-xadc-axi.pdf
谢谢和RegardsBalkrishan -----------------------------------------------
---------------------------------------------请将帖子标记为
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以下为原文

check this XAPPs
https://www.xilinx.com/support/documentation/application_notes/xapp1183-zynq-xadc-axi.pdfThanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

嗨，
XADC AXI4Lite接口应该与AXI互连相连。
它们不应该显示为顶级端口。
它们显示为端口的事实意味着存在一些连接问题。
请重新检查您的连接。
您的BD是否通过了DRC检查？
问候。
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---- FPGA爱好者！-------------------------------------------
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以下为原文

Hi,
 
The XADC AXI4Lite interface is supposed to be connected with the AXI Interconnect. They should not show up as top-level ports.
 
The fact that they show up as ports, means that there is some connection problem.
Please re-check your connections. Did your BD pass the DRC check?
 
Regards.
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FPGA enthusiast!
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你好@balkris＆amp;
@ dpaul24，
感谢你的信息。
如果出现进一步的问题，我会更新线程。
问候，
西蒙



以下为原文

Hello @balkris & @dpaul24,
 
Thank you for the infos. I will update the thread in case of further problems.
 
Regards,
Simon