PLL将允许外围设备在16MHz下运行，而内核运行在32（或12/24或8/16）。我同意这似乎是一个小事情，但我认为，因为PLL是有外部来源反正它很少有门来运行HFIFT通过它（并重新路由一些信号和改变NDIV从4到2）。虽然表35-2显示Idd 2.2Ma在32 MHz无论PLL，我WoulD认为在较低的频率下运行外围设备有一定的省电。加上计时器延迟可以是两倍长（最大值）。
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The PLL would allow peripherals to run at 16MHz while the core runs at 32 (or 12/24 or 8/16). I would agree that this seems like a small thing, but I suppose since the PLL is there for external sources anyway it took very few gates to run the HFINT through it (and reroute a few signals and change the Ndiv from 4 to 2).
Although table 35-2 shows Idd as 2.2mA at 32MHz regardless of PLL, I would think there is some power saving from running peripherals at the lower freq. Plus timer delays could be twice as long (at max).
PLL将允许外围设备在16MHz下运行，而内核运行在32（或12/24或8/16）。我同意这似乎是一个小事情，但我认为，因为PLL是有外部来源反正它很少有门来运行HFIFT通过它（并重新路由一些信号和改变NDIV从4到2）。虽然表35-2显示Idd 2.2Ma在32 MHz无论PLL，我WoulD认为在较低的频率下运行外围设备有一定的省电。加上计时器延迟可以是两倍长（最大值）。
以上来自于百度翻译
以下为原文
The PLL would allow peripherals to run at 16MHz while the core runs at 32 (or 12/24 or 8/16). I would agree that this seems like a small thing, but I suppose since the PLL is there for external sources anyway it took very few gates to run the HFINT through it (and reroute a few signals and change the Ndiv from 4 to 2).
Although table 35-2 shows Idd as 2.2mA at 32MHz regardless of PLL, I would think there is some power saving from running peripherals at the lower freq. Plus timer delays could be twice as long (at max).
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