嗨,MQ ~,
我的问题是,我能用32位FIFO使用哪种引脚来满足这个需求?
取决于你的需要。你需要从奴隶FIFO读和写传输吗?
我认为当FIFO被配置时,这些引脚完全可用——GPIO 23;GPIO 25;GPIO 26;GPIO 27;GPIO 45。我是理发师吗?
对。您可以用IOMATRAIX函数或GPIOORILE来配置它们。
是否可以使用I2S引脚(GPIO 50-52;57)作为GPIO?
是的,这是可能的。只需使用FX3SDK的GPIOORIDLE函数即可。
是否有可能使用SPI来满足第三点的要求?
如果您重新配置GPIF在16和32位精细使用硬件SPI,那么您可以使用任何GPIO引脚的芯片选择和写保护线的两个闪存模块。当数据通过SPI传输时,必须设置CS和WP的问题。这意味着用发送/接收SPI函数进行字节计数。如果Flash模块需要对每个传输的断言和CS或WP的重新断言,那么如果您在单次传输模式中全部完成,则需要LunGe时间。因为您必须使用GPIO SET/CLR做CS和WP,需要1微秒来设置或CLR。
当做
隆皮
以上来自于百度翻译
以下为原文
Hi mq~,
>> My question is which pins I could use with 32bit FIFO to meet this demands?
depends on your needs. Do you need read and write transfers in slave fifo?
>> I think those pins are fully available when FIFO is configured - GPIO 23; GPIO 25; GPIO 26; GPIO 27; GPIO 45. Am I rigth?
yes. You may configure them with the IOMatrix function or the GpioOverride.
>> Is it possible to use I2S pins (GPIO 50-52; 57) as GPIO also?
yes it is possible. Just use the GpioOverride function of the FX3 SDK.
>> Is it any possibility to use SPI to meet the requirements of the third point?
If you reconfigure the GPIF between 16 and 32 bit fine to use hardware SPI, then you be able to use any GPIO pin for chip select and write protect lines of the two flash modules. Problems may if CS and WP has to be set while data is transferring through SPI. That means with the function Send-/Receive SPI you have a argument with byte count. If the flash module needs assertion and re-assertion of CS or WP for each transfer, then it takes longe time if you do all in single transfer mode. Because you have to use a GPIO set/clr to do CS and WP wich takes ~1micro second to set or clr.
Regards
lumpi
嗨,MQ ~,
我的问题是,我能用32位FIFO使用哪种引脚来满足这个需求?
取决于你的需要。你需要从奴隶FIFO读和写传输吗?
我认为当FIFO被配置时,这些引脚完全可用——GPIO 23;GPIO 25;GPIO 26;GPIO 27;GPIO 45。我是理发师吗?
对。您可以用IOMATRAIX函数或GPIOORILE来配置它们。
是否可以使用I2S引脚(GPIO 50-52;57)作为GPIO?
是的,这是可能的。只需使用FX3SDK的GPIOORIDLE函数即可。
是否有可能使用SPI来满足第三点的要求?
如果您重新配置GPIF在16和32位精细使用硬件SPI,那么您可以使用任何GPIO引脚的芯片选择和写保护线的两个闪存模块。当数据通过SPI传输时,必须设置CS和WP的问题。这意味着用发送/接收SPI函数进行字节计数。如果Flash模块需要对每个传输的断言和CS或WP的重新断言,那么如果您在单次传输模式中全部完成,则需要LunGe时间。因为您必须使用GPIO SET/CLR做CS和WP,需要1微秒来设置或CLR。
当做
隆皮
以上来自于百度翻译
以下为原文
Hi mq~,
>> My question is which pins I could use with 32bit FIFO to meet this demands?
depends on your needs. Do you need read and write transfers in slave fifo?
>> I think those pins are fully available when FIFO is configured - GPIO 23; GPIO 25; GPIO 26; GPIO 27; GPIO 45. Am I rigth?
yes. You may configure them with the IOMatrix function or the GpioOverride.
>> Is it possible to use I2S pins (GPIO 50-52; 57) as GPIO also?
yes it is possible. Just use the GpioOverride function of the FX3 SDK.
>> Is it any possibility to use SPI to meet the requirements of the third point?
If you reconfigure the GPIF between 16 and 32 bit fine to use hardware SPI, then you be able to use any GPIO pin for chip select and write protect lines of the two flash modules. Problems may if CS and WP has to be set while data is transferring through SPI. That means with the function Send-/Receive SPI you have a argument with byte count. If the flash module needs assertion and re-assertion of CS or WP for each transfer, then it takes longe time if you do all in single transfer mode. Because you have to use a GPIO set/clr to do CS and WP wich takes ~1micro second to set or clr.
Regards
lumpi
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