输入时钟和MMCM输出时钟之间的延迟

当你说时钟之间的“延迟”时，你不是指一个相位延迟，而是在输入时钟开始运行和输出时钟变得有效之间的延迟......（至少这是我从你的时间看到的
图）。
这是对MMCM的真实行为进行建模。
MMCM是一个基于PLL的时钟生成模块，需要时间来锁定输入时钟。
锁定所需的最长时间在数据表中指定 - 例如，对于Kintex-7，它位于DS189，表37，MMCM_Tlockmax中，指定为100us。
在您的模拟中，您只能看到10us;
仿真模型没有模拟完整的100us，因为这浪费了仿真时间......
但是高达100us是真实的，您需要在系统设计中考虑它。
当锁定完成时，MMCM将发出LOCKED输出;
通常使用MMCM的！LOCKED输出作为MMCM输出时钟上运行的逻辑的复位生成机制的输入。
Avrum
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以下为原文

When you say "delay" between the clocks, you don't mean a phase delay, but a delay between the time the input clock starts running and the output clock becomes valid... (at least that is what I see from your timing diagram).
 
This is modelling the real behavior of the MMCM. The MMCM is a PLL based clock generation block that takes time to lock to the incoming clock. The maximum time required for the lock is specified in the datasheet - for example for a Kintex-7 it is in DS189, Table 37, MMCM_Tlockmax, which is specified as 100us. In your simulation you are seeing only 10us; the simulation model does not model the full 100us since that wastes simulation time...
 
But the up to 100us is real and you need to account for it in your system design. The MMCM will issue the LOCKED output when lock is achieved; it is customary to use the !LOCKED output of the MMCM as an input to the reset generation mechanism for the logic that is running on the of the MMCM output clocks.
 
Avrum
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当你说时钟之间的“延迟”时，你不是指一个相位延迟，而是在输入时钟开始运行和输出时钟变得有效之间的延迟......（至少这是我从你的时间看到的
图）。
这是对MMCM的真实行为进行建模。
MMCM是一个基于PLL的时钟生成模块，需要时间来锁定输入时钟。
锁定所需的最长时间在数据表中指定 - 例如，对于Kintex-7，它位于DS189，表37，MMCM_Tlockmax中，指定为100us。
在您的模拟中，您只能看到10us;
仿真模型没有模拟完整的100us，因为这浪费了仿真时间......
但是高达100us是真实的，您需要在系统设计中考虑它。
当锁定完成时，MMCM将发出LOCKED输出;
通常使用MMCM的！LOCKED输出作为MMCM输出时钟上运行的逻辑的复位生成机制的输入。
Avrum



以下为原文

When you say "delay" between the clocks, you don't mean a phase delay, but a delay between the time the input clock starts running and the output clock becomes valid... (at least that is what I see from your timing diagram).
 
This is modelling the real behavior of the MMCM. The MMCM is a PLL based clock generation block that takes time to lock to the incoming clock. The maximum time required for the lock is specified in the datasheet - for example for a Kintex-7 it is in DS189, Table 37, MMCM_Tlockmax, which is specified as 100us. In your simulation you are seeing only 10us; the simulation model does not model the full 100us since that wastes simulation time...
 
But the up to 100us is real and you need to account for it in your system design. The MMCM will issue the LOCKED output when lock is achieved; it is customary to use the !LOCKED output of the MMCM as an input to the reset generation mechanism for the logic that is running on the of the MMCM output clocks.
 
Avrum

嗨@avrumw，
感谢您的回复。
嗯你是对的。
输入时钟锁定和输出时钟锁定之间的时间在实际上与模拟不同。
虽然，对于kintex-7（-2速度等级）它最大100 us，这个时间是随机的，即我实际上不知道如何控制这个时间。
我只能测量一下，知道实际上是什么时候。
输入和输出时钟之间的锁定时间差：
锁定信号指示clk_out端口何时输出时钟信号。
另外，对于我的情况，我使用两个时钟向导，第一个向导的输出时钟是第二个时钟向导的输入。
这就是我有两个锁定信号的原因。
对于MMCM相移，所有相位递增/递减必须在锁定信号变为输出信号的高电平之前完成。
谢谢
Rappy



以下为原文

Hi @avrumw,
Thanks for your reply.
 
Yeah you are right. The time between input clock locked and output clock locked is different in practical than simulation. Although, for kintex-7 (-2 speed grade) it is maximum 100 us , this time is random i.e. I actually don't know how to control this time. I just can measure to know what is the time actually.
The lock time difference between input and output clock:

The lock signal indicate when the clk_out port can out clock signal. Besides, for my case, I am using two clock wizard the output clock of the first wizard is the input of the second clock wizard. That's why I have two lock signal. For the MMCM phase shifting, all phase increment/decrement have to be done before the lock signal goes high for the output signal. 
 
Thanks
Rappy