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[问答]

请问如何设计一个6位随机数发生器

你好,
我需要设计一个6位随机数发生器。
我找不到任何解决这个问题的好方法。
如果你能帮助我,请尽快帮我。
谢谢。

以上来自于谷歌翻译


以下为原文

Hello,

I need to design a 6 bit random number generator. I can't find any good solutions for this problem. If you can help me, please do so as soon as pos***ile. thanks.

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曾玲娟

2019-4-29 07:17:13
注意,存在TRNG(真随机数发生器)和PRNG(伪随机数发生器)和导数威廉希尔官方网站 。
我见过不同的方法,包括线性反馈移位寄存器,环形振荡器,各种组合反馈威廉希尔官方网站 等。
许多这些威廉希尔官方网站 也可能无法很好地模拟 - 取决于它们的结构。
实施可能会有所不同,具体取决于您的申请,测试水平以及您要满足的人数(例如***评估和认证与宠物项目)。
这是我缓存的一些资源,其中许多我之前在google中找到过。
http://www.xilinx.com/support/documentation/application_notes/xapp052.pdf(高效移位寄存器,LFSR计数器和长伪随机序列发生器)http://www.xilinx.com/cn/support/documentation/application_notes
/xapp211.pdf(使用SRL宏的PN生成器)http://www.ht-lab.com/freecores/mt32/mersenne.html(Mersenne Twister,MT32,Xilinx FPGA的伪随机数生成器)
http://www.cosic.esat.kuleuven.be/publications/article-790.pdf(FPG VENDOR AGNOSTIC TRUE RANDOM NUMBER GENERATOR)http://en.wikipedia.org/wiki/Hardware_random_number_generatorhttp://www.heliontech。
COM / random.htm
BT

以上来自于谷歌翻译


以下为原文

Note that there are TRNGs (true random number generators) and PRNGs (pseudo random number generators), and derivative circuits.

I've seen different approaches, including linear feedback shift registers, ring oscillators, various combinatorial feedback circuits, etc.

Many of these circuits also may not simulate well - depending on their construction.

The implementation will likely vary depending on your application, the level of testing,  and who you are trying to satisfy (e.g. government evaluation and certification versus pet project).

 

Here's a few resources I had cached, many of which I found earlier with google.

http://www.xilinx.com/support/documentation/application_notes/xapp052.pdf (Efficient Shift Registers, LFSR Counters, and Long Pseudo-Random Sequence Generators)
http://www.xilinx.com/support/documentation/application_notes/xapp211.pdf (PN Generators Using the SRL Macro)
http://www.ht-lab.com/freecores/mt32/mersenne.html (Mersenne Twister, MT32, Pseudo Random Number Generator for Xilinx FPGA)

http://www.cosic.esat.kuleuven.be/publications/article-790.pdf (FPGA VENDOR AGNOSTIC TRUE RANDOM NUMBER GENERATOR)
http://en.wikipedia.org/wiki/Hardware_random_number_generator
http://www.heliontech.com/random.htm

bt
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潘晶燕

2019-4-29 07:35:36
我有一篇白皮书描述了生成并行随机数的一种很好的方法。
它基于环形振荡器技术,但能够在采样时钟的每个时钟周期提供任意宽度的随机数。
我强烈推荐它,因为它已经构建,测试,数百亿比特被各种“真正的”随机测试套件检查,以表明它是一个很好的随机性来源(NIST等)。
给我发电子邮件:
austin@xilinx.com我将发送给您。
Austin Lesea主要工程师Xilinx San Jose

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I have a white paper that describes an excellent approach to generating a parallel random number.  It is based on ring oscillator techniques, but it is able to provide any width random number at each clock tick of the sampling clock.  I highly recommend it, as it has been built, tested, and tens of billions of bits were examind by the various "true" random test suites to show it was an excellent source of randomness (NIST, etc.).
 
email me at:
 
austin@xilinx.com and I will send it to you.
 
Austin Lesea
Principal Engineer
Xilinx San Jose
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云甫太

2019-4-29 07:40:45
嗨, 
我需要在verilog / vhdl中为我的项目生成字节方式的随机地址生成器逻辑,如果你可以与我共享代码将会很棒。
已发送邮件来自我的sudhanshu.sxna@gmail.com
提前致谢
sudhanshu

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Hi,
 
   I Need to generate byte wise random address generator logic in verilog/vhdl for my project, It will be great if you can pls share the code with me.  have sent a mail an email from my sudhanshu.sxna@gmail.com
 
Thanks in advance 
 
sudhanshu
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李晟才

2019-4-29 07:50:16
你好
我试图使用两个rocs一个d触发器和一个8位计数器来制作一个8位trng。
请帮帮我。

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以下为原文

hello 
I am trying to make a 8 bit trng using two rocs one d flip flop and a 8 bit counter.
 
please help me out.
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