嗨，
你写的内容有些令人困惑，如果在某些部分没有错误的话。
1）FF不在LUT内。
LUT和FF都是切片内的独立部分。
除此之外，切片还具有其他组件，如进位链和路由多路复用器。
切片及其组件的数量和功能选项可能因不同的FPGA系列而异
2）信号的转换速率是输出驱动功率和连接路由和输入的（容性）负载的结果。
因此，输入信号的变化速度不会超过其自身的压摆率。
您描述的行为是一种更复杂的情况。
让我试着改写一下。
当您从具有高压摆率的某个源驱动输入，并且该信号比输入的信号的回转速度快时，输入信号将不会被威廉希尔官方网站
识别。
现在回到原始的海报问题：时钟输入上缓慢变化的信号怎么样？
通常，FF上的时钟输入表现得像任何普通的CMOS输入。
有效的输入电压范围在数据手册中定义，如果您的信号在这些电压范围之间的禁区内保持太长，您的输入可能会开始振荡。
（取决于硅片上使用的技术）。
但！
FPGA上的FF通常连接到由特殊时钟驱动器驱动的时钟网络。
它们具有适当的转换速率，可在0和1之间快速变化，因此不会产生负面影响。
您正在将时钟信号连接到专用时钟输入（IBUFG），这些输入连接到特殊时钟网络驱动器（BUFG）或DCM。
我不知道这些IBUFG是否具有能够将慢速上升时钟（例如施密特触发器）的影响降至最低的任何能力。
但另一个问题出现了：
这种输入允许的最大上升时间是多少？
如果没有在数据表中找到一个困难的问题，但也许一些假设是有帮助的。
（我将只使用粗略的估计数字，而不是真正的前沿利润）
1）FPGA可以在1MHz时钟下运行良好（今天速度非常慢）。
2）要获得一个漂亮的方波，应达到10次谐波（傅立叶频率合成），这将导致信号上升时间足以满足FPGA的要求。
（粗略估计：100 ns）
因此，如果你有一个周期小于100 ns的时钟信号，它的上升时间比我上面的脆弱计算要好，即使它只是一个正弦波。
一旦信号达到'0'和'1'的电压余量，输入驱动器将切换并在FPGA内部产生精细的时钟边沿，事情变得非常快。
;-)
另外需要考虑的事情：
您谈到了高失真时钟信号：您专注于低通效果，将矩形渲染为类似正弦波的信号。
这没问题。
但是当失真涉及尖峰，弹跳和这样的东西时，FF可能会将这些视为额外的时钟边沿并在不需要的时间触发，从而导致威廉希尔官方网站
出现故障。
有一个很好的综合
Eilert
以上来自于谷歌翻译
以下为原文
Hi,
what you wrote is a little confusing, if not wrong in some parts.
1) The FFs are not inside the LUTs.
LUTs and FFs are both separate parts inside a slice.
Besides these a slice has other components like a carry chain and routing muxes.
The number and functional options of a slice and its components may vary between different FPGA Famlies
2) The slew rate of a signal is the result of the driving power of an output and the (capacitive) load of the connected routes and inputs. Therefore the incoming signal can't change faster than it's own slew rate.
The behavior you describe is a more complex situation. Let me try to rephrase it.
When you have an input driven from some source with a high slew rate, and that signal is faster than the slewrates of the signals BEHIND that input, the incoming signal will not be recognized by the circuit.
Now back to the original posters question: What about slow changing signals on Clock inputs?
In general, a clock input on a FF behaves like any ordinary CMOS input.
The valid input voltage ranges are defined in the data sheets, and if your signal stays too long in the forbidden area between these voltage ranges, your input may begin to oscillate. (depends on the technology used on the silicon).
BUT!
The FFs on an FPGA are normally connected to a Clock net, driven by special clock drivers. These have appropriate slew rates to change fast enough between 0 and 1, so there will be no negative effects.
You are connecting your Clock signal to dedicated clock inputs (IBUFG), and these go to special clock net drivers (BUFG) or DCMs.
I don't know if these IBUFGs have any capabilities that would minimize the effects of slow rising clocks (e.g. Schmitt trigger).
But another question arises:
What is the allowed maximum rise time for such an input? If not to be found in the datasheets a dificult question, but maybe some assumptions are helpful. (I will use only rough estimated numbers, not real cutting edge margins)
1) A FPGA can run fine with a 1MHz Clock (which is quite slow for today).
2) To have a nice square wave the 10th harmonic should be reached (Fourier Frequency synthesis ) and this will result in a signal rise time that is sufficient for an FPGA. (rough estimation: 100 ns)
So if you have a clock signal with a period of less than 100 ns it will have a better rise time than in my flimsy calculation above, even if it is just a sine wave. Once the signal hit's the voltage margins for '0' and '1' the input driver wil toggle and generate a fine clock edge inside the FPGA, where things go really fast. ;-)
Another thing to consider:
You talked about high distorted Clock signals: You focussed on Low pass effects, rendering the rectangle to a sinewave-like signal. This is no problem. But when the distortions involve spikes, bouncing and such stuff, The FFs may see these as additional clock edges and become triggered at unwanted times, thus causing malfunction in your circuit.
Have a nice synthesis
Eilert
嗨，
你写的内容有些令人困惑，如果在某些部分没有错误的话。
1）FF不在LUT内。
LUT和FF都是切片内的独立部分。
除此之外，切片还具有其他组件，如进位链和路由多路复用器。
切片及其组件的数量和功能选项可能因不同的FPGA系列而异
2）信号的转换速率是输出驱动功率和连接路由和输入的（容性）负载的结果。
因此，输入信号的变化速度不会超过其自身的压摆率。
您描述的行为是一种更复杂的情况。
让我试着改写一下。
当您从具有高压摆率的某个源驱动输入，并且该信号比输入的信号的回转速度快时，输入信号将不会被威廉希尔官方网站
识别。
现在回到原始的海报问题：时钟输入上缓慢变化的信号怎么样？
通常，FF上的时钟输入表现得像任何普通的CMOS输入。
有效的输入电压范围在数据手册中定义，如果您的信号在这些电压范围之间的禁区内保持太长，您的输入可能会开始振荡。
（取决于硅片上使用的技术）。
但！
FPGA上的FF通常连接到由特殊时钟驱动器驱动的时钟网络。
它们具有适当的转换速率，可在0和1之间快速变化，因此不会产生负面影响。
您正在将时钟信号连接到专用时钟输入（IBUFG），这些输入连接到特殊时钟网络驱动器（BUFG）或DCM。
我不知道这些IBUFG是否具有能够将慢速上升时钟（例如施密特触发器）的影响降至最低的任何能力。
但另一个问题出现了：
这种输入允许的最大上升时间是多少？
如果没有在数据表中找到一个困难的问题，但也许一些假设是有帮助的。
（我将只使用粗略的估计数字，而不是真正的前沿利润）
1）FPGA可以在1MHz时钟下运行良好（今天速度非常慢）。
2）要获得一个漂亮的方波，应达到10次谐波（傅立叶频率合成），这将导致信号上升时间足以满足FPGA的要求。
（粗略估计：100 ns）
因此，如果你有一个周期小于100 ns的时钟信号，它的上升时间比我上面的脆弱计算要好，即使它只是一个正弦波。
一旦信号达到'0'和'1'的电压余量，输入驱动器将切换并在FPGA内部产生精细的时钟边沿，事情变得非常快。
;-)
另外需要考虑的事情：
您谈到了高失真时钟信号：您专注于低通效果，将矩形渲染为类似正弦波的信号。
这没问题。
但是当失真涉及尖峰，弹跳和这样的东西时，FF可能会将这些视为额外的时钟边沿并在不需要的时间触发，从而导致威廉希尔官方网站
出现故障。
有一个很好的综合
Eilert
以上来自于谷歌翻译
以下为原文
Hi,
what you wrote is a little confusing, if not wrong in some parts.
1) The FFs are not inside the LUTs.
LUTs and FFs are both separate parts inside a slice.
Besides these a slice has other components like a carry chain and routing muxes.
The number and functional options of a slice and its components may vary between different FPGA Famlies
2) The slew rate of a signal is the result of the driving power of an output and the (capacitive) load of the connected routes and inputs. Therefore the incoming signal can't change faster than it's own slew rate.
The behavior you describe is a more complex situation. Let me try to rephrase it.
When you have an input driven from some source with a high slew rate, and that signal is faster than the slewrates of the signals BEHIND that input, the incoming signal will not be recognized by the circuit.
Now back to the original posters question: What about slow changing signals on Clock inputs?
In general, a clock input on a FF behaves like any ordinary CMOS input.
The valid input voltage ranges are defined in the data sheets, and if your signal stays too long in the forbidden area between these voltage ranges, your input may begin to oscillate. (depends on the technology used on the silicon).
BUT!
The FFs on an FPGA are normally connected to a Clock net, driven by special clock drivers. These have appropriate slew rates to change fast enough between 0 and 1, so there will be no negative effects.
You are connecting your Clock signal to dedicated clock inputs (IBUFG), and these go to special clock net drivers (BUFG) or DCMs.
I don't know if these IBUFGs have any capabilities that would minimize the effects of slow rising clocks (e.g. Schmitt trigger).
But another question arises:
What is the allowed maximum rise time for such an input? If not to be found in the datasheets a dificult question, but maybe some assumptions are helpful. (I will use only rough estimated numbers, not real cutting edge margins)
1) A FPGA can run fine with a 1MHz Clock (which is quite slow for today).
2) To have a nice square wave the 10th harmonic should be reached (Fourier Frequency synthesis ) and this will result in a signal rise time that is sufficient for an FPGA. (rough estimation: 100 ns)
So if you have a clock signal with a period of less than 100 ns it will have a better rise time than in my flimsy calculation above, even if it is just a sine wave. Once the signal hit's the voltage margins for '0' and '1' the input driver wil toggle and generate a fine clock edge inside the FPGA, where things go really fast. ;-)
Another thing to consider:
You talked about high distorted Clock signals: You focussed on Low pass effects, rendering the rectangle to a sinewave-like signal. This is no problem. But when the distortions involve spikes, bouncing and such stuff, The FFs may see these as additional clock edges and become triggered at unwanted times, thus causing malfunction in your circuit.
Have a nice synthesis
Eilert
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