MSP430F6726A晶振不起振问题

各位大神，小弟新使用MSP430F6726A做开发，遇到晶振不起振问题，头疼不已，还请各位大神指点迷津。
主要问题：使用32.768kHz晶振接MCU24,25管脚（XIN,XOUT），根据规格书使用12pF的匹配电容，晶振不起振，更换3pF,6pF,9pF,15pF,22pF,30pF,47pF匹配电容还是不起振，询问ti技术人员也没给出具体解决办法，基本上也是从PCB布线，电容匹配方面给分析的，但都已试过，没起作用，由于此款MCU自带晶振，外部晶振不起振会转到内部晶振起振，以下是源码部分从TI官网上弄得：
void  Systerm_Clock_init(void)
{
volatile unsigned int i;
PJDIR |= BIT0 | BIT1 | BIT3;                      //ACLK, MCLK, SMCLK set out to pins
PJSEL |= BIT0 | BIT1 | BIT3;                      //PJ.0,1,3 for debugging purposes.

// Setup UCS
// Loop until XT1 fault flag is cleared
do
{
   UCSCTL7 &= ~XT1LFOFFG;                         //Clear XT1 fault flags
} while (UCSCTL7 & XT1LFOFFG);                      //Test XT1 fault flag

UCSCTL6 &= ~(XT1OFF);                               //XT1 On
UCSCTL6 |= XCAP_3;                                  //Internal load cap
__bic_SR_register(SCG0);                            // Enable the FLL control loop
UCSCTL0 = 0x0000;                                  //Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5;                               //Select DCO range 16MHz operation
UCSCTL2 = FLLD_0 + 511;                            //(N + 1) * FLLRef = Fdco=(487 + 1) * 32768 =15990784Hz= 16MHz
__bic_SR_register(SCG0);                            //Enable the FLL control loop
__delay_cycles(600000);                            //32 x 32 x 16 MHz / 32,768 Hz = 500000 = MCLK cycles for DCO to settle

UCSCTL4 |= SELA_0+SELS_3+SELM_3;                   //Set ACLK = XT1，SCLK=MCLK=DCOCLK=16M
UCSCTL6 &= ~(XT1DRIVE_3);                         //XT1 stable, reduce drive strength*/

}
实在不清楚到底哪出问题了，还望使用过此芯片的大神给指导一二。